Video apparatus, notably video decoder, and process for memory control in such an apparatus

• US 20020126225A1
• Filed: 02/25/2002
• Published: 09/12/2002
• Est. Priority Date: 03/09/2001
• Status: Active Grant

• Current Assignee: Thomson Licensing (Vantiva SA)
• Original Assignee: Thomson Licensing (Vantiva SA)
• Inventors: Creusot, Daniel, Ritz, Edouard, Faye, Daniel
• Granted Patent: US 7,154,559 B2
• Time in Patent Office: Days
• US Class Current: 348/714
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: H04N 21/426 Internal components of the client ; Characteristics thereof H04N5/44 takes precedence
• CPC Class Codes: H04N 21/434 Disassembling of a multiplex stream, e.g. demultiplexing audio and video streams, extraction of additional data from a video stream; Remultiplexing of multiplex streams; Extraction or processing of SI; Disassembling of packetised elementary stream demultiplexing of data packets for data networks, e.g. RTP/UDP H04L65/00
• CPC Class Codes: H04N 21/4435 Memory management allocation of memory to service a request G06F9/5016; addressing or allocating within memory systems or architectures G06F12/02

Abstract

A video apparatus has a digital decoder having a first memory on an internal bus and linked to an OSD circuit and to a second memory via a main bus.

The video apparatus comprises means for realising a DMA transfer between the first memory and the second memory.

A process for controlling such a video apparatus is also described.

Claims

1. A video apparatus with a digital decoder having a first memory on an internal bus and linked to an OSD circuit and to a second memory via a main bus,

the video apparatus comprising means for realising a DMA transfer between the first memory and the second memory.

2. A video apparatus according to claim 1, wherein a CPU is connected to the main bus.

3. A video apparatus according to claim 2, wherein the second memory is used by the CPU.

4. A video apparatus according to claim 1, wherein the first memory is a Video RAM and wherein the second memory is a CPU RAM.

5. A video apparatus according to claim 1, wherein the digital decoder is connected to a digital front-end.

6. A process for controlling a video apparatus with a digital decoder having a first memory on an internal bus and linked to an OSD circuit and to a second memory via a main bus, comprising the step of realising a DMA transfer between the first memory and the second memory via the digital decoder.

7. A process according to claim 6, comprising the following steps:

issuing a request for the OSD circuit to use more than a given size in the second memory,

realising a DMA transfer from the second memory to the first memory.

8. A process according to claim 7, with the further steps of:

issuing a request for the OSD circuit to use data in the first memory,

copying via a DMA transfer data from the second memory to the first memory;

realising a DMA transfer of the requested data from the first memory to the second memory.