Multiple oxide thicknesses for merged memory and logic applications
First Claim
1. A semiconductor device comprising:
- a top device formed on a top surface of a silicon wafer, wherein the top surface has a (110) crystal plane orientation, the top device having a top gate separated from the top surface by a top gate oxide; and
a trench device formed on a trench wall of the silicon wafer, wherein the trench wall has a (100) crystal plane orientation, the trench device having a trench gate separated from the trench wall by a trench gate oxide, wherein a thickness of the top gate oxide is different from a thickness of the trench gate oxide.
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Abstract
Structures are provided for multiple oxide thicknesses on a single silicon wafer. In particular, structures are provided for multiple gate oxide thicknesses on a single chip. The chip can include circuitry including but not limited to the memory and logic technologies. These structures for multiple oxide thickness on a single silicon wafer can be used in conjunction with existing fabrication and processing techniques with minimal or no added complexity. One structure includes a top layer of SiO2 on a top surface of a silicon wafer and a trench layer of SiO2 on a trench wall of the silicon wafer. The trench wall of the silicon wafer has a different order plane-orientation than the top surface. The thickness of the top layer is different from a thickness of the trench layer.
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Citations
45 Claims
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1. A semiconductor device comprising:
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a top device formed on a top surface of a silicon wafer, wherein the top surface has a (110) crystal plane orientation, the top device having a top gate separated from the top surface by a top gate oxide; and
a trench device formed on a trench wall of the silicon wafer, wherein the trench wall has a (100) crystal plane orientation, the trench device having a trench gate separated from the trench wall by a trench gate oxide, wherein a thickness of the top gate oxide is different from a thickness of the trench gate oxide. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A semiconductor device comprising:
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a top oxide layer formed on a top surface of a silicon wafer, wherein the top surface has a (110) crystalline orientation and wherein the top oxide layer has a top oxide thickness; and
a trench oxide layer formed on a trench wall of the silicon wafer, wherein the trench wall has a (100) crystalline orientation and wherein the trench oxide layer has a trench oxide thickness that is different from the top oxide thickness. - View Dependent Claims (9, 10, 11, 13, 14, 15, 17, 18, 19)
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12. A semiconductor device, comprising:
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a top surface of a silicon wafer, the top surface having a (110) crystalline plane orientation;
a trench wall in the silicon wafer, the trench wall having a (511) crystalline plane orientation;
a top oxide layer on the top surface; and
a trench oxide layer on the trench wall, wherein the top oxide layer has a different thickness than the trench oxide layer.
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16. A semiconductor device comprising:
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a logic device formed on a top surface of a silicon wafer, wherein the top surface has a (111) crystalline plane orientation, the logic device having a logic gate separated from the top surface by a logic gate oxide; and
a flash memory cell formed on a trench wall of the silicon wafer, wherein the trench wall has a (110) crystalline plane orientation, the flash memory cell having a flash gate separated from the trench wall by a flash gate oxide, wherein a thickness of the logic gate oxide is different from a thickness of the flash gate oxide.
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20. A semiconductor device, comprising:
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a top layer of SiO2 on a top surface of a silicon wafer; and
a trench layer of SiO2 on a trench wall of the silicon wafer, wherein the trench wall has a different order plane-orientation than the top surface, and wherein the top layer has a different thickness than the trench layer. - View Dependent Claims (21, 22, 23, 25, 26, 27, 28, 29)
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24. A semiconductor device, comprising:
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a logic device formed on a top surface of a silicon wafer, wherein the top surface has a (110) crystal plane orientation, the logic device having a logic gate separated from the top surface by a logic gate oxide; and
an EEPROM (Electronically Erasable Programmable Read Only Memory) device formed on a trench wall of the silicon wafer, the EEPROM device having an EEPROM gate separated from the trench wall by a EEPROM gate oxide, wherein the trench wall has a different order plane-orientation than top surface and wherein a thickness of the logic gate oxide is different from a thickness of the EEPROM gate oxide.
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30. An electronic system comprising:
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a processor; and
an integrated circuit coupled to the processor, the integrated circuit including;
a top device formed on a top surface of a silicon wafer, wherein the top surface has a (110) crystal plane orientation, the top device having a top gate separated from the top surface by a top gate oxide; and
a trench device formed on a trench wall of the silicon wafer, wherein the trench wall has a (100) crystal plane orientation, the trench device having a trench gate separated from the trench wall by a trench gate oxide, wherein a thickness of the top gate oxide is different from a thickness of the trench gate oxide. - View Dependent Claims (31, 32, 33, 34, 36, 37, 38, 39, 40)
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35. An electronic system comprising:
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a processor; and
a flash memory device including;
a logic device formed on a top surface of a silicon wafer, wherein the top surface has a (111) crystal plane orientation, the logic device having a logic gate separated from the top surface by a logic gate oxide; and
a flash memory cell formed on a trench wall of the silicon wafer, wherein the trench wall has a (110) crystal plane orientation, the flash memory cell having a flash gate separated from the trench wall by a flash gate oxide, wherein a thickness of the flash gate oxide is different from the logic gate oxide.
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41. An electronic system comprising:
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a processor; and
a decode circuit, comprising;
a logic circuit formed on a top surface of a silicon wafer, wherein the top layer has a (110) crystal plane orientation, the logic circuit having a logic gate separated from the top layer by a logic gate oxide; and
an EEPROM (Electronically Erasable Programmable Read Only Memory) device formed on a trench wall of the silicon wafer, the EEPROM device having an EEPROM gate separated from the trench wall by a EEPROM gate oxide, wherein the trench wall has a different order plane-orientation than top surface and wherein a thickness of the EEPROM gate oxide is different from a thickness of the logic gate oxide. - View Dependent Claims (42, 43, 44, 45)
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Specification