Multiple oxide thicknesses for merged memory and logic applications

• US 20020127884A1
• Filed: 05/06/2002
• Published: 09/12/2002
• Est. Priority Date: 08/31/1999
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Forbes, Leonard, Noble, Wendell P.
• Granted Patent: US 6,887,749 B2
• Time in Patent Office: Days
• US Class Current: 438/787
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/28211 in a gaseous ambient using an oxygen or a water vapour, e.g. RTO, possibly through a layer H01L21/28194 and H01L21/28202 take precedence
• CPC Class Codes: H01L 21/31662 of silicon in uncombined form
• CPC Class Codes: H01L 21/823462 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823857 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H10B 12/0383 wherein the transistor is vertical
• CPC Class Codes: H10B 12/05 Making the transistor
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells
• CPC Class Codes: H10B 12/50 Peripheral circuit region structures
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

Methods are provided for fabricating multiple oxide thicknesses on a single silicon wafer. Methods are provided to form multiple gate oxide thicknesses on a single chip wherein the chip can include circuitry encompassing a range of technologies including but not limited to the memory and logic technologies. These methods can be used in conjunction with existing fabrication and processing techniques with minimal or no added complexity. Methods for forming a semiconductor device include forming a top layer of SiO₂ on a top surface of a silicon wafer. A trench layer of SiO₂ is also formed on a trench wall of the silicon wafer. The trench wall of the silicon wafer has a different order plane-orientation than the top surface. Additionally, the formation of the top and trench layers of SiO₂ are such that a thickness of the top layer is different from a thickness of the trench layer.

Claims

1. A method comprising:

forming a top layer of SiO₂ on a top surface of a silicon wafer, wherein the top surface has a (100) crystal plane orientation, such that the top layer has a top thickness; and

forming a trench layer of SiO₂ on a trench wall of the silicon wafer, wherein the trench wall has a (110) crystal plane orientation, such that the trench layer has a trench thickness that is different from the top thickness.

2. The method of claim 1, wherein forming the trench layer of SiO₂ includes forming the trench layer of SiO₂ that has a thickness that is approximately 30% thicker than the top layer of SiO₂.

3. The method of claim 1, wherein forming the top layer of SiO₂ includes forming the top layer as a gate oxide of a logic device.

4. The method of claim 3, wherein forming the top layer of SiO₂ includes forming the logic device wherein the logic device has an operating voltage of less than 2.5 volts.

5. The method of claim 1, wherein forming the trench layer of SiO₂ includes forming the trench layer as a gate oxide of a DRAM cell.

6. The method of claim 5, wherein forming the trench layer of SiO₂ includes forming the DRAM cell wherein the DRAM cell has an operating voltage of less than 3.5 volts.

7. The method of claim 1, wherein forming the top layer of SiO₂ and forming the trench layer of SiO₂ includes forming the top layer of SiO₂ and forming the trench layer of SiO₂ simultaneously during a linear growth period.

8. The method of claim 1, wherein forming the top layer of SiO₂ includes forming the top layer as a gate oxide of a logic device, and wherein forming the trench layer of SiO₂ includes forming the trench layer as a gate oxide of a DRAM cell.

9. The method of claim 1, wherein forming the top layer of SiO₂ includes forming the top layer as a gate oxide of a logic device, wherein the logic device has an operating voltage of less than 2.5 volts, and wherein forming the trench layer of SiO₂ includes forming a trench layer as a gate oxide of a DRAM cell, wherein the DRAM cell has an operating voltage of less than 3.5 volts.

10. A method comprising:

forming a top device on a top surface of a silicon wafer, wherein the top surface has a (100) crystal plane orientation and the top device includes a top gate separated from the top surface by a top gate oxide; and

forming a trench device on a trench wall of a trench in the silicon wafer, wherein the trench wall has a (110) crystal plane orientation and the trench device includes a trench gate separated from the trench wall by a trench gate oxide, such that a thickness of the top gate oxide is different from a thickness of the trench gate oxide.

11. The method of claim 10, wherein forming the top device includes wet oxidizing the top surface at a temperature of approximately 800°

C.

12. The method of claim 10, wherein forming the trench device includes wet oxidizing the trench surface at a temperature of approximately 800°

C.

13. The method of claim 10, wherein forming the top device and forming the trench device includes simultaneously forming the top gate oxide and the trench gate oxide during a linear growth period.

14. The method of claim 10, wherein forming the top gate oxide includes forming the top gate oxide as a gate oxide of a logic device.

15. The method of claim 10, wherein forming the trench gate oxide includes forming the trench gate oxide as a gate oxide of a DRAM cell.

17. The method of claim 16, wherein forming the top device on the top surface of the silicon wafer includes forming the thickness of the top gate oxide to approximately 70 Angstroms, and wherein forming the trench device on the trench wall of the trench includes forming the thickness of the trench gate oxide to approximately 100 Angstroms.

18. The method of claim 16, wherein the top surface and the trench wall are formed by simultaneous thermal oxidation, and where the thermal oxidation is selected from wet oxidation and dry oxidation.

19. The method of claim 16, wherein forming the top device and forming the trench device includes simultaneously forming the top gate oxide and the trench gate oxide during a linear growth period.

20. The method of claim 16, the method further including:

forming a stacked capacitor DRAM (Dynamic Random Access Memory) cell in the trench.

16. A method comprising:

forming a top device on a top surface of a silicon wafer, wherein the top surface has a (100) crystal plane orientation and wherein the top device includes a top gate separated from the top surface by a thermally formed top gate oxide;

forming a trench in the silicon wafer such that a trench wall forms with a (110) crystal plane orientation; and

forming a trench device on the trench wall, the trench device including a trench gate separated from the trench wall by a thermally formed trench gate oxide, wherein the top gate oxide has a thickness which is different from a thickness of the trench gate oxide.

21. A method comprising:

forming a top layer of SiO₂ on a top surface of a silicon wafer, wherein the top surface has a (111) crystal plane orientation, such that the top layer has a top thickness; and

forming a trench layer of SiO₂ on a trench wall of the silicon wafer, wherein the trench wall has a (110) crystal plane orientation, such that the trench layer has a trench thickness that is different from the top thickness of the top layer.

22. The method of claim 21, wherein forming the trench layer of SiO₂ on the trench wall includes forming the trench layer of SiO₂ that has a thickness that is approximately 30% thicker than a thickness of the top layer of SiO₂.

23. The method of claim 21, wherein forming the top layer of SiO₂ and forming the trench layer of SiO₂ includes forming the top layer of SiO₂ and forming the trench layer of SiO₂ simultaneously during a linear growth period.

24. The method of claim 21, the method further including:

forming an NVRAM (Non-Volatile Random Access Memory) device at the trench layer of SiO₂.

25. The method of claim 21, the method further including:

forming a floating gate device at the trench layer of SiO₂.

27. The method of claim 26, wherein simultaneously forming the top oxide layer on the top surface and forming the trench oxide layer on the trench wall includes dry oxidizing the top surface at a temperature of approximately 800°

C.

28. The method of claim 26, the method further including:

forming a floating gate device at the trench oxide layer.

29. The method of claim 26, the method further including:

forming a floating gate at the trench oxide layer; and

forming a control gate at the floating gate.

26. A method comprising:

forming a top surface of a silicon wafer with a (111) crystalline plane orientation;

forming a trench in the silicon wafer, wherein a trench wall has a (110) crystalline plane orientation; and

simultaneously forming a top oxide layer on the top surface and forming a trench oxide layer on the trench wall, during a linear growth period, wherein the top oxide layer has a different thickness than the trench oxide layer.

30. A method comprising:

forming a top layer of SiO₂ on a top surface of a silicon wafer, wherein the top surface has a (111) crystalline orientation, such that the top layer has a top thickness; and

forming a trench layer of SiO₂ on a trench wall of the silicon wafer, wherein the trench wall has a (110) crystalline orientation, such that the trench layer has a trench thickness that is different from the top thickness of the top layer, wherein forming the top layer of SiO₂ and forming the trench layer of SiO₂ includes forming the top layer of SiO₂ and forming the trench layer of SiO₂ simultaneously during a linear growth period, and wherein forming the trench layer of SiO₂ on the trench wall includes forming the trench layer of SiO₂ that has a thickness that is approximately 30% thicker than a thickness of the top layer of SiO₂.

31. The method according to claim 30, the method further including:

forming a CMOS logic circuit that includes the top layer of SiO₂ on the top surface of the silicon wafer.

32. The method according to claim 30, the method further including:

forming a CMOS logic circuit that includes the top layer of SiO₂ on the top surface of the silicon wafer; and

forming a NVRAM (non-volatile random access memory) device on the trench layer of SiO₂.

33. A method comprising:

forming a logic device on a top surface of a silicon wafer, wherein the top surface has a (100) crystal plane orientation and wherein the logic device includes a logic gate separated from the top surface by a logic gate oxide; and

forming an EEPROM (Electronically Erasable Programmable Read Only Memory) device on a trench wall of the silicon wafer, wherein the trench wall has a different order plane-orientation than the top surface and wherein the EEPROM device includes an EEPROM gate separated from the trench wall by an EEPROM gate oxide, wherein the logic gate oxide has a thickness which is different from a thickness of the EEPROM gate oxide.

34. The method of claim 33, the method further including:

forming a programmable logic array that includes the logic device and the EEPROM.