RFID interrogator having customized radio parameters with local memory storage

• US 20020127970A1
• Filed: 12/07/2001
• Published: 09/12/2002
• Est. Priority Date: 12/07/2000
• Status: Active Grant

• Current Assignee: Intermec IP Corporation (Honeywell International Inc.)
• Original Assignee: Intermec IP Corporation (Honeywell International Inc.)
• Inventors: Martinez, Rene D.
• Granted Patent: US 7,039,359 B2
• Time in Patent Office: Days
• US Class Current: 455/41.2
• CPC Class Codes: G01S 13/825 with exchange of information between interrogator and responder
• CPC Class Codes: G06K 7/0008 General problems related to the reading of electronic memory record carriers, independent of its reading method, e.g. power transfer

Abstract

An RFID interrogator has a receiver/transmitter architecture that accounts for the variation in tolerances of radio system electrical components. The RFID interrogator includes a memory in which is stored desired initial condition data of the receiver/transmitter architecture, and this initial condition data is used upon initialization of the RFID interrogator to define the operational condition of the RFID interrogator. Each individual RFID interrogator may contain unique initial condition data corresponding to the particular component tolerances of that radio system.

Claims

1. An apparatus for interrogating an RFID tag, comprising:

a radio adapted to communicate RF signals with said RFID tag, said radio including a receiver portion and a transmitter portion;

a processor operatively coupled to said radio and providing control signals defining operational parameters of said radio; and

a memory accessible by said processor and containing at least one data value used to set said operational parameters.

2. The apparatus of claim 1, wherein said transmitter portion further comprises an amplifier subsystem adapted to be operated in a saturated condition.

3. The apparatus of claim 2, wherein said processor comprises at least one digital potentiometer defining a DC voltage supplied to said amplifier subsystem that controls an output power level of said amplifier subsystem, and said at least one data value defines an initial setting of said at least one digital potentiometer, wherein said at least one data value is selected to achieve said saturated condition of said amplifier subsystem.

4. The apparatus of claim 3, wherein said amplifier subsystem further comprises at least one power amplifier having a gain determined by said at least one digital potentiometer of said processor.

5. The apparatus of claim 3, wherein said amplifier subsystem further comprises first and second quadrature hybrids and first and second power amplifiers, said first quadrature hybrid splitting a modulated signal into two signals differing in phase by 90°

and provided to said first and second power amplifiers, respectively, said second quadrature hybrid thereafter recombining amplified output signals from said first and second amplifiers.

6. The apparatus of claim 5, wherein said amplifier subsystem further comprises a resistor termination connected to at least one of said first and second quadrature hybrids for attenuating reflected power from at least one of said first and second power amplifiers.

7. The apparatus of claim 1, wherein said memory further comprises a non-volatile memory.

8. The apparatus of claim 1, wherein said memory further comprises a CMOS electrically erasable programmable read only memory (EEPROM).

9. The apparatus of claim 1, wherein said memory is allocated into a plurality of memory blocks with at least one of said plurality of memory blocks including a cyclic redundancy code (CRC).

10. The apparatus of claim 9, wherein at least one of said plurality of memory blocks is reserved for identification of said radio.

11. The apparatus of claim 9, wherein at least one of said plurality of memory blocks is reserved for said at least one data value.

13. The method of claim 12, wherein said determining step further comprises sweeping an input power level applied to said amplifier from low to high in order to determine said saturated output power level for said amplifier.

14. The method of claim 12, wherein said recording step further comprises recording said at least one digital potentiometer value in a non-volatile memory.

15. The method of claim 14, further comprising allocating said memory into a plurality of memory blocks with at least one of said plurality of memory blocks including a cyclic redundancy code (CRC).

16. The method of claim 15, further comprising reserving at least one of said plurality of memory blocks for identification of said radio.

17. The method of claim 15, further comprising reserving at least one of said plurality of memory blocks for said at least one digital potentiometer value.

18. The method of claim 14, wherein said generating step further comprises retrieving said at least one digital potentiometer value from said non-volatile memory during an initialization of said apparatus.

19. The method of claim 12, wherein said amplifier further comprises at least one power amplifier, and said determining step further comprises determining a gain of said at least one power amplifier.

12. In an apparatus for interrogating an RFID tag comprising a radio for communicating RF signals and having an amplifier, and a processor operatively coupled to said radio and providing control signals defining operational parameters of said amplifier, a method for setting said operational parameters comprises:

determining a bias condition of said amplifier sufficient to achieve a saturated output power level for said amplifier;

recording a value of at least one digital potentiometer of said processor corresponding to said determined bias condition; and

generating said control signals using said recorded digital potentiometer value.