Clock control method and information processing device employing the clock control method

• US 20020129292A1
• Filed: 03/08/2002
• Published: 09/12/2002
• Est. Priority Date: 03/08/2001
• Status: Active Grant

• Current Assignee: Socionext Inc.
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Kaneko, Keisuke
• Granted Patent: US 7,000,135 B2
• Time in Patent Office: Days
• US Class Current: 713/400
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3237 by disabling clock generation or distribution
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

In an information processing device including a processing circuit that performs processing in synchronization with a clock, and a clock supply control circuit that controls supply of the clock to the processing circuit, the number of cycles required from start of execution of processing in the processing circuit until output of a result of the processing is extracted, the extracted number of cycles is transferred to the clock supply control circuit, the supply of the clock is started when the processing is started in the processing circuit, and the supply of the clock to the processing circuit is stopped when the supply of the clock with the number of cycles is completed. Thus, a clock control method and an information processing device employing the clock control method are provided that allow power consumption to be reduced without impairing an execution efficiency of pipeline processing.

Claims

1. A clock control method employed in an information processing device, the information processing device including:

a processing circuit that performs processing in synchronization with a clock; and

a clock supply control circuit that controls supply of the clock to the processing circuit,

the clock control method comprising;

extracting a number of cycles required from start of execution of processing in the processing circuit until output of a result of the processing;

transferring the extracted number of cycles to the clock supply control circuit;

starting the supply of the clock when the processing is started in the processing circuit; and

stopping the supply of the clock to the processing circuit when the supply of the clock with the number of cycles is completed.

2. The clock control method according to claim 1, wherein the number of cycles is not less than the minimum number of cycles from the start of execution of the processing until the output of the result of the processing, and is less than the number of cycles in the case where the clock is supplied at all times.

19. An information processing device employing the clock control method according to claim 1.

3. A clock control method employed in an information processing device, the information processing device including:

first and second processing circuits that perform processing in synchronization with a clock; and

a clock supply control circuit that controls supply of the clock to the first processing circuit,

wherein processing in the first processing circuit and processing in the second processing circuit can be carried out independently and simultaneously, and a result of the processing in the first processing circuit is inputted to the second processing circuit,

the clock control method comprising;

extracting a number of cycles required from start of execution of the processing in the first processing circuit until input of the result of the processing to the second processing circuit;

transferring the extracted number of cycles to the clock supply control circuit;

starting the supply of the clock when the processing is started in the first processing circuit; and

stopping the supply of the clock to the first processing circuit after the supply of the clock with the number of cycles is completed.

20. An information processing device employing the clock control method according to claim 3.

4. A clock control method employed in an information processing device, the information processing device including:

first and second processing circuits that perform processing in synchronization with a clock; and

a clock supply control circuit that controls supply of the clock to the first processing circuit,

wherein a result of the processing in the first processing circuit is inputted to the second processing circuit,

in the case where first processing and second processing are executed successively in the first processing circuit, and the first processing circuit starts executing the second processing simultaneously when the second processing device starts executing third processing with respect to the result of the processing in the first processing circuit as an input thereto, the clock control method comprising;

(1) extracting a first number of cycles required for the execution of the processing in the first processing circuit;

(2) transferring the first number of cycles to the clock supply control circuit;

(3) starting the supply of the clock when the processing is started in the first processing circuit;

(4) determining whether or not the second processing circuit can start processing, when the supply of the clock with the first number of cycles is completed;

(5) extracting the second number of cycles required for the execution of the second processing in the first processing circuit;

(6) transferring the second number of cycles to the clock supply control circuit;

(7) inputting a result of the processing in the first processing circuit to the second processing circuit in the case where it is determined at the operation (4) that the processing can be started; and

(8) starting the supply of the clock with the second number of cycles to the first processing circuit so as to start the second processing in the first processing circuit, in the case where it is determined at the operation (4) that the processing can be started.

21. An information processing device employing the clock control method according to claim 4.

5. A clock control method employed in an information processing device that is capable of pipeline processing of an instruction, the method comprising:

extracting a number of cycles required for execution of an instruction at an execution stage;

controlling supply of a clock to a circuit belonging to the execution stage; and

transferring the extracted number of cycles,

wherein the supply of the clock is carried out for the number of cycles since start of the execution of the instruction at the execution stage.

6. The clock control method according to claim 5, wherein in the operation of extracting the number of cycles, as to each instruction, the number of cycles for execution at the execution stage is specified, so that the number of cycles for execution is extracted as the number of cycles simultaneously when an instruction code is decoded and a type of the instruction is determined.

7. The clock control method according to claim 6, wherein in the operation of extracting the number of cycles, an execution cycle number field is provided that specifies the number of cycles for execution at the execution stage with a bit code of the instruction, so that the number of cycles for execution at the execution stage is extracted as the number of cycles from the execution cycle number field simultaneously when an instruction code is decoded and a type of the instruction is determined.

8. The clock control method according to claim 6, wherein in the operation of extracting the number of cycles, all instructions executed by the information processing device are divided into groups according to the numbers of cycles for execution at the execution stage, group identification numbers are given to the groups, and a group identification number field in which the group identification number is set is provided in each instruction code, so that the group identification number is extracted and the number of cycles for execution corresponding to the group identification number is extracted as the number of cycles from the group identification number field, simultaneously when the instruction code is decoded and a type of the instruction is determined.

9. The clock control method according to claim 6, wherein in the operation of extracting the number of cycles, in the case where a variable-length instruction is processed, the number of cycles for execution at the execution stage is specified as to each instruction word length of an instruction code, so that the number of cycles for execution is extracted as the number of cycles from the instruction word length of the decoded instruction simultaneously when the instruction code is decoded and a type of the instruction is determined.

22. An information processing device employing the clock control method according to claim 5.

10. A clock control method employed in an information processing device that is capable of pipeline processing of an instruction, the method comprising:

extracting the number of cycles required for execution of an instruction at an execution stage;

controlling supply of a clock to a circuit belonging to the execution stage;

transferring the number of cycles; and

selecting either starting the supply of the clock at start of the execution of the instruction at the execution stage or not,

wherein in the case where the starting of the supply of the clock is selected in the clock supply selecting operation, the supply of the clock with the number of cycles is started at the start of the execution of the instruction at the execution stage in the clock supply controlling operation.

11. The clock control method according to claim 10, wherein in the clock supply selecting operation, a clock supply permission bit is provided in an instruction code that is indicative of whether the supply of the clock is to be started at the start of the execution of the instruction at the execution stage, so that information on whether the supply of the clock is to be started is extracted from the clock supply permission bit upon decoding of the instruction code.

12. The clock control method according to claim 11, wherein a dependence relationship between a first instruction and a second instruction that are successive instructions is analyzed, and in the case where the second instruction refers to an execution result of the first instruction, the clock supply permission bit is set in an ON state.

14. The clock control method according to claim 13, wherein the clock supply selecting operation includes a sub-operation of determining a state of the first instruction being executed at the stage next to the execution stage, and a dependence relationship between a second instruction to be executed at the execution stage and the first instruction,

wherein:

in the case where the second instruction is dependent on an execution result of the first instruction, not starting the supply of the clock with the number of cycles required for execution of the second instruction at the execution stage before completion of the execution of the first instruction is selected; and

in the case where the second instruction is not dependent on the completion of the execution of the first instruction, carrying out the supply of the clock with the number of cycles required for the execution at the execution stage is selected.

16. The clock control method according to claim 15, wherein the supply of the clock to each of the stage is controllable at each of the stages in the pipeline, and the supply of the clock to each of the stage can be suspended except when an instruction is being executed at each of the stages.

17. The clock control method according to claim 16, wherein in the case where a low-speed operation bit is provided in an instruction code and an instruction in which the low-speed operation bit is set is executed at the execution stage, the supply of the clock with the number of cycles is started after it is detected that execution of a preceding instruction is completed at all the stages behind the execution stage.

18. The clock control method according to claim 15, wherein an execute-form code is generated according to a program described in a high-level language, the method further comprising an operation of:

specifying whether or not a low-speed operation is to be carried out, with program description in the high-level language,

wherein in the case where the program description that specifies with the high-level language that the low-speed operation is to be carried out is converted into an execute-form code, a clock supply start permission bit is set in an ON state.

23. An information processing device employing the clock control method according to claim 10.

24. An information processing device employing the clock control method according to claim 13.

13. A clock control method employed in an information processing device capable of pipeline processing of an instruction, the method comprising:

extracting a number of cycles required for execution of an instruction at an execution stage;

controlling supply of a clock to a circuit belonging to the execution stage;

transferring the number of cycles;

selecting either starting the supply of the clock at start of the execution of the instruction at the execution stage or not; and

determining a state of a stage next to the execution stage,

wherein in the case where the starting of the supply of the clock is selected in the clock supply selecting operation and it is determined in the next stage state determining operation that the next stage is ready for execution, the supply of the clock with the number of cycles is started at the start of the execution of the instruction at the execution stage in the clock supply controlling operation.

15. A clock control method employed in an information processing device capable of pipeline processing of an instruction, the method comprising:

extracting the number of cycles required for execution of an instruction at an execution stage;

controlling supply of a clock to a circuit belonging to the execution stage;

transferring the number of cycles;

selecting either starting the supply of the clock at start of the execution of the instruction at the execution stage or not; and

detecting completion of execution of instructions at all stages behind the execution stage;

wherein in the case where the starting of the supply of the clock is selected in the clock supply selecting operation and it is detected that the execution of instructions is completed at all the stages behind the execution stage, the supply of the clock with the number of cycles is started at the start of the execution of the instruction at the execution stage in the clock supply controlling operation.

25. An information processing device employing the clock control method according to claim 15.