Layout method of latch-up prevention circuit of a semiconductor device

• US 20020130332A1
• Filed: 08/28/2001
• Published: 09/19/2002
• Est. Priority Date: 03/12/2001
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kwak, Choong-Keun, Cho, Beak-Hyung
• Granted Patent: US 6,657,264 B2
• Time in Patent Office: Days
• US Class Current: 257/147
• CPC Class Codes: H01L 27/0266 using field effect transistors as protective elements
• CPC Class Codes: H01L 27/0921 Means for preventing a bipolar, e.g. thyristor, action between the different transistor regions, e.g. Latchup prevention

Abstract

A layout method is provided for a latch-up prevention circuit of a semiconductor memory device which includes the steps of: arranging a cell array at substantially the middle of the device; placing peripheral circuits next to both sides of the cell array; placing a plurality of pads on both sides of the cell array between the peripheral circuits and both edges of the device; and arranging guard rings beneath the plurality of pads. The layout method further includes a plurality of ESD protection transistors disposed axially along the direction as the plurality of pads between the plurality of pads and an edge of the device. And each of guard ring is a NWELL guard ring, and connected to a supply voltage and ground.

Claims

1. A layout method of a latch-up prevention circuit of a semiconductor memory device, comprising the steps of:

arranging a plurality of pads at an edge of the device; and

arranging a guard ring beneath the plurality of pads.

2. The layout method, as defined in claim 1, further comprising a plurality of ESD protection transistors disposed axially along the direction as the plurality of pads and between the plurality of pads and the edge of the device.

3. The layout method, as defined in claim 1, wherein the guard ring is a NWELL guard ring.

4. The layout method, as defined in claim 1, wherein the guard ring is connected to the edge of the device along the parallel direction as the plurality of pads.

5. The method, as defined in claim 1, wherein the guard ring is connected to one of a supply voltage and ground.

6. A layout method of a latch-up prevention circuit of a semiconductor memory device comprising the steps of:

arranging a cell array at substantially the middle of the device;

placing peripheral circuits next to both sides of the cell array;

placing a plurality of pads on both sides of the cell array between the peripheral circuits and both edges of the device; and

arranging guard rings beneath the plurality of pads.

7. The layout method, as defined in claim 6, further comprising a plurality of ESD protection transistors along the parallel direction as the plurality of pads between the plurality of pads and an edge of the device.

8. The layout method, as defined in claim 6, wherein each of the guard ring is a NWELL guard ring.

9. The layout method, as defined in claim 6, wherein each of the guard ring is connected to an edge of the device along the parallel direction as the plurality of pads.

10. The method, as defined in claim 6, wherein each of the guard ring is connected to one of a supply voltage and ground.

11. A semiconductor memory device having a latch-up prevention circuit, comprising:

a cell array disposed substantially at the middle of the device;

a plurality of peripheral circuits disposed next to both sides of the cell array;

a plurality of pads disposed at all sides of the cell array between the peripheral circuits and edges of the device; and

guard rings disposed beneath the plurality of pads.

12. The device of claim 11, further comprising a plurality of ESD protection transistors disposed axially along the axial direction as the plurality of pads and between the plurality of pads and an edge of the device.

13. The device of claim 11, wherein each of the guard rings is a NWELL guard ring.

14. The device of claim 11, wherein each of the guard rings is connected each other.

15. The device of claim 11, wherein each of the guard rings is connected to one of a supply voltage and ground.