Low leakage input protection device and scheme for electrostatic discharge

• US 20020130364A1
• Filed: 03/15/2001
• Published: 09/19/2002
• Est. Priority Date: 03/15/2001
• Status: Active Grant

• Current Assignee: Microsemi Corporation (Microchip Technology Incorporated)
• Original Assignee: Microsemi Corporation (Microchip Technology Incorporated)
• Inventors: Comeau, Alain R.
• Granted Patent: US 6,842,318 B2
• Time in Patent Office: Days
• US Class Current: 257/355
• CPC Class Codes: H01L 27/0266 using field effect transistors as protective elements
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

ESD input protection device uses a transistor (82) with the source terminal (100) connected to the input (12) from these source (18) to provide an alternate path for discharge. By having the input (12) imprint connected to the source (100) rather than the drain (102) and the substrate (104) and gate (103) terminals connected to a reference so that a decrease in the leakage current (I_s) is realized as the source voltage (18) is increased over a range. The protection scheme is suitable for use with smaller device geometries such as 0.18 CMOS operating at 1½ to 2 volts.

Claims

1. A device for electrostatic discharge input protection comprising:

a transistor with gate, source, drain and substrate terminals;

an input signal terminal coupled to said source terminal of said transistor;

a reference point coupled to said gate and substrate terminals of said transistor; and

a output signal terminal coupled to said drain terminal of said transistor;

where the leakage current of said transistor is reduced to a sub-threshold level while an increasing source voltage applied at said source terminal reduces the gate-to-source voltage and reduces its threshold voltage.

2. The device of claim 1 wherein said reference point comprises the ground for a specific electrostatic discharge application.

3. The device of claim 1 wherein said reference point is 0 volts.

4. The device of claim 1 wherein said reference point comprises V_SS.

5. The device of claim 1 wherein said source voltage is a few 100 mV.

6. The device of claim 5 wherein said leakage current is approximately 10⁻

14 A/um.

7. The device of claim 1 wherein said transistor is an NMOS transistor.

8. The device of claim 1 wherein said transistor is a PMOS transistor.

9. A low leakage Electrostatic Discharge (ESD) protection scheme comprising:

a plurality of low operating voltage devices, each device having at least one device input for receiving an input signal;

a plurality of input terminals for coupling an input signal to a device via a corresponding device input;

a plurality of transistors with gate, substrate, source and drain terminals, each transistor providing an alternate pathway via a source terminal for signals from said plurality of input terminals; and

a reference coupled to corresponding gate and substrate terminals of said plurality of input protection transistors; and

a source voltage driving both said source terminals of said input protection transistors and said inputs of said low operating voltage devices;

wherein ESD protection is achieved by coupling the source terminals of said plurality of transistors to said plurality of input terminals thereby limiting the leakage current of each of said transistors to a sub-threshold level even as said source voltage increases.

10. The protection scheme of claim 9 wherein said plurality of low operating voltage devices are CMOS.

11. The protection scheme of claim 9 wherein said reference point comprises a ground reference.

12. The protection scheme of claim 9 wherein said reference point is 0 volts.

13. The protection scheme of claim 9 wherein said reference point comprises V_SS for said low voltage operating devices and said plurality of transistors.

14. The protection scheme of claim 9 wherein said source voltage is limited to a few 100 mV.

15. The protection scheme of claim 14 wherein the resulting leakage current from said source voltage is approximately 10⁻

14 A/um.

16. The protection scheme of claim 9 wherein said plurality of transistors are NMOS type.

17. The protection scheme of claim 9 wherein said plurality of transistors are PMOS type.

19. The IC of claim 18 wherein said plurality of input protection transistors are NMOS type.

20. The IC of claim 18 wherein said plurality of input protection transistors are PMOS type.

21. The IC of claim 18 wherein said devices, terminals, input paths, and input protection transistors are contained on a single semiconductor chip.

22. The IC of claim 18 wherein said reference point is a ground reference point associated with said devices.

23. The IC of claim 18 wherein said reference point is a 0 volt point associated with said devices.

24. The IC of claim 18 wherein said reference point is tied to said V_SS.

18. A low voltage Integrated Circuit (IC) with on-board ESD input protection comprising:

a plurality of low operating voltage devices, at least one reference point, one supply voltage point and a plurality of input terminals coupled to said devices;

a plurality of input paths for coupling input signals to said devices via said input terminals; and

a plurality of input protection transistors with gate, substrate, source, and drain terminals arranged between said input paths and said devices, each source terminal coupled to a corresponding input path, each gate and substrate terminal coupled to a reference point;

wherein a leakage current of said input protection transistors is controlled to a sub-threshold level over a range of voltages applied to each source terminal of said input protection transistors.