SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

• US 20020130374A1
• Filed: 08/04/1999
• Published: 09/19/2002
• Est. Priority Date: 03/05/1997
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: UENO, SHUICHI, OKUMURA, YOSHINORI, MAEDA, SHIGENOBU, MAEGAWA, SHIGETO
• Granted Patent: US 6,492,690 B2
• Time in Patent Office: Days
• US Class Current: 257/392
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/49 comprising different types of peripheral transistor

Abstract

According to a semiconductor device and a method of manufacturing the same, a trade-off relationship between threshold values and a diffusion layer leak is eliminated and it is not necessary to form gate oxide films at more than one stages. Since impurity dose are different from each other between gate electrodes (4A to 4C) of N-channel type MOS transistors (T41 to T43), impurity concentration in the gate electrodes (4A to 4C) are different from each other. The impurity concentration in the gate electrodes are progressively lower in the order of higher threshold values which are expected.

Claims

1. A semiconductor device including at least one of a first to a third types of transistors on a semiconductor substrate,

a transistor of said first type comprises:

a first semiconductor layer of a first conductivity type which is formed in a surface of said semiconductor substrate;

a first channel dope layer of the first conductivity type which is formed selectively in said first semiconductor layer; and

a first control electrode which is formed at a position which faces said first channel dope layer, on said first semiconductor layer,

a transistor of said second type comprises;

a second semiconductor layer of the first conductivity type which is formed in the surface of said semiconductor substrate;

a second channel dope layer of the first conductivity type which is formed selectively in said second semiconductor layer; and

a second control electrode which is formed at a position which faces said second channel dope layer, on said second semiconductor layer,

a transistor of said third type comprises;

a third semiconductor layer of the first conductivity type which is formed in the surface of said semiconductor substrate;

a third channel dope layer of the first conductivity type which is formed selectively in said third semiconductor layer; and

a third control electrode which ss formed at a position which faces said third channel dope layer, on said third semiconductor layer, and

at least one of said first to said third control electrodes internally includes an impurity layer of the second conductivity type having a concentration distribution in the direction of depth.

2. The semiconductor device of claim 1, wherein said transistor of said first type comprises:

a pair of first semiconductor regions of the second conductivity type formed selectively and independently of each other within said first semiconductor layer; and

a first gate oxide film which is formed on said first semiconductor layer between said pair of first semiconductor regions,

said first control electrode is formed on said first gate oxide film,

said first channel dope layer is formed between said pair of first semiconductor regions within said first semiconductor layer,

said transistor of said second type comprises;

a pair of second semiconductor regions of the second conductivity type formed selectively and independently of each other within said second semiconductor layer; and

a second gate oxide film which is formed on said second semiconductor layer between said pair of second semiconductor regions,

said second control electrode is formed on said second gate oxide film,

said second channel dope layer is formed between said pair of second semiconductor regions within said second semiconductor layer,

said transistor of said third type comprises;

a pair of third semiconductor regions of the second conductivity type formed selectively and independently of each other within said third semiconductor layer; and

a third gate oxide film which is formed on said third semiconductor layer between said pair of third semiconductor regions,

said third control electrode is formed on said third gate oxide film,

said third channel dope layer is formed between said pair of third semiconductor regions within said third semiconductor layer,

said first, said second and said third control electrodes include a first, a second and a third impurity layers, respectively, which have different impurity concentrations from each other,

said first to said third gate oxide films have the same thickness, and

said first to said third channel dope layers have the same impurity concentration.

3. The semiconductor device of claim 1, wherein said transistor of said first type comprises:

a pair of first semiconductor regions of the second conductivity type formed selectively and independently of each other within said first semiconductor layer; and

a first gate oxide film which is formed on said first semiconductor layer between said pair of first semiconductor regions,

said first control electrode is formed on said first gate oxide film,

said first channel dope layer is formed between said pair of first semiconductor regions within said first semiconductor layer,

said transistor of said second type comprises;

a pair of second semiconductor regions of the second conductivity type formed selectively and independently of each other within said second semiconductor layer; and

a second gate oxide film which is formed on said second semiconductor layer between said pair of second semiconductor regions,

said second control electrode is formed on said second gate oxide film,

said second channel dope layer is formed between said pair of second semiconductor regions within said second semiconductor layer,

said transistor of said third type comprises;

a pair of third semiconductor regions of the second conductivity type formed selectively and independently of each other within said third semiconductor layer;

a third gate oxide film which is formed on said third semiconductor layer between said pair of third semiconductor regions;

a floating gate electrode which is formed on said third gate oxide film; and

an inter-layer insulation film which is formed on said floating gate electrode,

said third control electrode is formed on said inter-layer insulation film,

said third channel dope layer is formed between said pair of third semiconductor regions within said third semiconductor layer,

said first, said second and said third control electrodes include a first, a second and a third impurity layers, respectively, which have different impurity concentrations from each other,

said first and said second gate oxide films have the same thickness which is a first thickness but said third gate oxide film has a second thickness which is thicker than said first thickness, and

said first to said third channel dope layers have the same impurity concentration.

4. The semiconductor device of claim 1, wherein said transistor of said first type comprises:

a pair of first semiconductor regions of the second conductivity type formed selectively and independently of each other within said first semiconductor layer; and

a first gate oxide film which is formed on said first semiconductor layer between said pair of first semiconductor regions,

said first control electrode is formed on said first gate oxide film,

said first channel dope layer is formed between said pair of first semiconductor regions within said first semiconductor layer,

said transistor of said second type comprises;

a pair of second semiconductor regions of the second conductivity type formed selectively and independently of each other within said second semiconductor layer; and

a second gate oxide film which is formed on said second semiconductor layer between said pair of second semiconductor regions,

said second control electrode is formed on said second gate oxide film,

said second channel dope layer is formed between said pair of second semiconductor regions within said second semiconductor layer,

said transistor of said third type comprises;

a pair of third semiconductor regions of the second conductivity type formed selectively and independently of each other within said third semiconductor layer; and

a third gate oxide film which is formed on said third semiconductor layer between said pair of third semiconductor regions,

said third control electrode is formed on said third gate oxide film,

said third channel dope layer is formed between said pair of third semiconductor regions within said third semiconductor layer,

said first and said second control electrodes include a first and a second impurity layers, respectively, which have the same impurity concentration with each other,

said third control electrode includes a third impurity layer whose concentration is lower than those of said first and said second impurity layers,

said first to said third gate oxide films have the same thickness, and

said first and said third channel dope layers have the same impurity concentration.

5. The semiconductor device of claim 1, wherein said transistor of said first sype comprises:

a pair of first semiconductor regions of the second conductivity type formed selectively and independently of each other within said first semiconductor layer; and

a first gate oxide film which is formed on said first semiconductor layer between said pair of first semiconductor regions,

said first control electrode is formed on said first gate oxide film,

said first channel dope layer is formed between said pair of first semiconductor regions within said first semiconductor layer,

said transistor of said second type comprises;

a pair of second semiconductor regions of the second conductivity type formed selectively and independently of each other within said second semiconductor layer; and

a second gate oxide film which is formed on said second semiconductor layer between said pair of second semiconductor regions,

said second control electrode is formed on said second gate oxide film,

said second channel dope layer is formed between said pair of second semiconductor regions within said second semiconductor layer,

said transistor of said third type comprises;

a pair of third semiconductor regions of the second conductivity type formed selectively and independently of each other within said third semiconductor layer;

a third gate oxide film which is formed on said third semiconductor layer between said pair of third semiconductor regions;

a floating gate electrode which is formed on said third gate oxide film; and

an inter-layer insulation film which is formed on said floating gate electrode,

said third control electrode is formed on said inter-layer insulation film,

said third channel dope layer is formed between said pair of third semiconductor regions within said third semiconductor layer,

said first and said third control electrodes include a first and a third impurity layers, respectively, which have the same impurity concentration with each other,

said second control electrode includes a second impurity layer whose concentration is lower than those of said first and said third impurity layers,

said first and said second gate oxide films have the same thickness which is a first thickness but said third gate oxide film has a second thickness which is thicker than said first thickness, and

said first to said third channel dope layers have the same impurity concentration.

6. A method of manufacturing a semiconductor device in which there are at least one of a first to a third types of transistors on a semiconductor substrate, comprising the steps of:

(a) forming a first to a third semiconductor layers of the first conductivity type at positions within a surface of said semiconductor substrate at which said first to said third types of transistors are formed;

(b) selectively forming a first, a second and a third channel dope layers of the first conductivity type within said first, said second and said third semiconductor layers, respectively, by ion implantation; and

(c) forming a first to a third control electrodes at positions facing said first to said third channel dope layers on said first to said third semiconductor layers, wherein

said step (c) of forming said first to said third control electrodes includes a step of forming an impurity layer of the first conductivity type which has a concentration distribution in the direction of depth within at least one of said first to said third control electrodes.

7. The method of manufacturing a semiconductor device of claim 6, wherein said step (c) comprises the steps of:

forming an oxide film on said first to said third semiconductor layers;

forming a first conductive layer on said oxide film;

implanting an impurity of the second conductivity type into said first conductive layer at a dose n1 to thereby form a second conductive layer which has a concentration distribution in the direction of depth within said first conductive layer;

masking over said second conductive layer at a position at which said third type of transistor is formed and implanting an impurity of the second conductivity type into said not-masked second conductive layer at a dose n2 to thereby form a third conductive layer which has a concentration distribution in the direction of depth within said second conductive layer;

masking over said third and said second conductive layers at positsons at which said second and said third type of transistors are formed and implanting an impurity of the second conductivity type into said not-masked third conductive layer at a dose n3 to thereby form a fourth conductive layer which has a concentration distribution in the direction of depth within said third conductive layer; and

selectively removing said second to said fourth conductive layers and said oxide film by patterning, to thereby form a first gate oxide film and a first control electrode on said first semiconductor layer, a second gate oxide film and a second control electrode on said second semiconductor layer, and a third gate oxide film and a third control electrode on said third semiconductor layer.

8. The method of manufacturing a semiconductor device of claim 6, wherein said step (c) comprises the steps of:

forming an oxide film on said first to said third semiconductor layers;

forming a first conductive layer on said oxide film;

patterning said first conductive layer and said oxide film to thereby selectively remove said first conductive layer and said oxide film;

selectively implanting an impurity of the second conductivity type into said first conductive layer at a dose n1 to thereby form a second conductive layer which has a concentration distribution in the direction of depth within said first conductive layer;

masking over said second conductive layer at a position at which said third type of transistor is formed and implanting an impurity of the second conductivity type into said not-masked second conductive layer at a dose n2 to thereby form a third conductive layer which has a concentration distribution in the direction of depth within said second conductive layer; and

masking over said third and said second conductive layers at positions at which said second and said third type of transistors are formed and implanting an impurity of the second conductivity type into said not-masked third conductive layer at a dose n3 to thereby form a fourth conductive layer which has a concentration distribution in the direction of depth within said third conductive layer.

9. The method of manufacturing a semiconductor device of claim 6, wherein said step (c) comprises the steps of:

forming a first oxide film having a first thickness on said first to said third semiconductor layers;

selectively forming a first conductive layer which ununiformly has an impurity of the second conductivity type on said first oxide film on said third semiconductor layer;

selectively forming an insulation film on said first conductive layer while removing said first oxide film at positions where said first and said second types of transistors are formed;

forming a second oxide film having a second thickness which is thinner than said first thickness on said first and said second semiconductor layer;

forming a second conductive layer on said second oxide film and said insulation film;

implanting an impurity of the second conductivity type into said second conductive layer at a dose n1 to thereby form a third conductive layer which has a concentration distribution in the direction of depth within said second conductive layer;

masking over said third conductive layer at a position at which said first type of transistor is formed and implanting an impurity of the second conductivity type into said not-masked third conductive layer at a dose n2 which remains to thereby form a fourth conductive layer which has a concentration distribution in the direction of depth within said third conductive layer;

masking over said third and said fourth conductive layers at positions at which said first and said third type of transistors are formed and implanting an impurity of the second conductivity type into said not-masked fourth conductive layer at a dose n3 which remains to thereby form a fifth conductive layer which has a concentration distribution in the direction of depth within said fourth conductive layer; and

selectively removing said third to said fifth conductive layers, said first and said second oxide films, and said insulation film by patterning, to thereby form a first gate oxide film and a first control electrode on said first semiconductor layer, a second gate oxide film and a second control electrode on said second semiconductor layer, and a third gate oxide film, a floating gate electrode, an inter-layer insulation film and a third control electrode on said third semiconductor layer.

10. The method of manufacturing a semiconductor device of claim 6, wherein said step (b) includes a step of forming said first and said third channel dope layers so that said first and said third channel dope layers have the same impurity concentration, and

said step (c) comprises the steps of:

forming an oxide film having a first thickness on said first to said third semiconductor layers;

forming a first conductive layer on said oxide film;

implanting an impurity of the second conductivity type into said first conductive layer at a dose n1 to thereby form a second conductive layer which has a concentration distribution in the direction of depth within said second conductive layer;

masking over said second conductive layer at a position at which said third type of transistor is formed and implanting an impurity of the second conductivity type into said not-masked second conductive layer at a dose n2 which remains to thereby form a third conductive layer which has a concentration distribution in the direction of depth within said second conductive layer;

selectively removing said second and said third conductive layers and said insulation film by patterning, to thereby form a first gate oxide film and a first control electrode on said first semiconductor layer, a second gate oxide film and a second control electrode on said second semiconductor layer, and a third gate oxide film and a third control electrode on said third semiconductor layer.

11. The method of manufacturing a semiconductor device of claim 6, wherein said step (c) comprises the steps of:

forming a first oxide film having a first thickness on said first to said third semiconductor layers;

selectively forming a first conductive layer which ununiformly has an impurity of the second conductivity type on said first oxide film on said third semiconductor layer;

selectively forming an insulation film on said first conductive layer while removing said first oxide film at positions where said first and said second types of transistors are formed;

forming a second oxide film having a second thickness which is thinner than said first thickness on said first and said second semiconductor layer;

forming a second conductive layer on said second oxide film and said insulation film;

implanting an impurity of the second conductivity type into said second conductive layer at a dose n1 to thereby form a third oxide film which has a concentration distribution in the direction of depth within said second conductive layer;

masking over said third conductive layer at a position at which said second type of transistor is formed and implanting an impurity of the second conductivity type into said not-masked third conductive layer at a dose n2 which remains to thereby form a fourth conductive layer which has a concentration distribution in the direction of depth within said third conductive layer; and

selectively removing said first, said third and said fourth conductive layers, said first and said second oxide films, and said insulation film by patterning, to thereby form a first gate oxide film and a first control electrode on said first semiconductor layer, a second gate oxide film and a second control electrode on said second semiconductor layer, and a third gate oxide film, a floating gate electrode, an inter-layer insulation film and a third control electrode on said third semiconductor layer.

13. The method of manufacturing a semiconductor device of claim 12, wherein said step (d) includes the steps of:

selectively forming a resist on said conductive layer on at least said first region among said first and said second regions and implanting said impurity around said resist by ion implantation; and

thermally diffusing said impurity which is implanted to thereby introduce said impurity into said conductive layer on at least said first region among said first and said second regions.

14. The method of manufacturing a semiconductor device of claim 12, wherein said step (d) includes the steps of:

selectively forming a resist on a portion extending from an edge portion of said conductive layer on at least said first region among said first and said second regions to said field oxide film and implanting said impurity into said conductive layer which is not covered with said resist by ion implantation; and

thermally diffusing said impurity which is implanted to thereby introduce said impurity into said conductive layer on at least said first region among said first and said second regions in such a manner that said impurity has a high concentration at a central portion taken in a plane direction but has a lower concentration with a distance toward said edge portion.

15. The method of manufacturing a semiconductor device of claim 12, wherein said step (c) includes a step of (c-1) stacking a first conductive layer which uniformly contains said impurity and said second conductive layer which does not contain said impurity to thereby form said conductive layers, and

said step (d) includes a step of diffusing said impurity naturally from said first conductive layer into said second conductive layer with respect to said first and said second conductive layers at least on said first region to thereby distribute said impurity.

16. The method of manufacturing a semiconductor device of claim 15, wherein said step (c-1) includes a step of forming a diffusion suppression film which suppresses a quantity of diffusion of said impurity between said first conductive layer and said second conductive layer.

12. A method of manufacturing a semiconductor device in which there are a first and a second types of transistors formed on a single semiconductor substrate, comprising the steps of:

(a) selectively forming a field oxide film on a main surface of said semiconductor substrate to thereby define a first and a second regions in which said first and said second types of transistors are formed;

(b) forming an oxide film on said first and said second regions and over said field oxide film;

(c) forming a conductive layer, which becomes a control electrode, on said oxide film; and

(d) introducing an impurity of the same conductivity type as that of a source/drain layer into said conductive layer on at least one of said first and said second regions.