ESD protection circuit with very low input capacitance for high-frequency I/O ports
First Claim
1. An electrostatic discharge (ESD) protection circuit with low input capacitance, suitable for an I/O pad, comprising a plurality of diodes, stacked and coupled between a first power line and the I/O pad, wherein during normal operation, the diodes are reverse-biased, and, when an ESD event occurs between a second power line and the I/O pad, the diodes are forward-biased to conduct ESD current.
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Accused Products
Abstract
The present invention proposes an ESD protection circuit with low input capacitance, suitable for an I/O pad. The ESD protection circuit includes a plurality of diodes and a power-rail ESD clamp circuit between power lines. The diodes are stacked and coupled between a first power line and the I/O pad. The ESD protection circuit between power lines is coupled between the first power line and a second power line. During normal operation, the diodes are reverse-biased and the ESD protection circuit between power lines is turned off. When an ESD event between the power line and the I/O pad occurs, the diodes are forward-biased, and the ESD protection circuit between power lines is turned on to conduct ESD current. The equivalent input capacitance of the ESD protection circuit of the present invention is very small, making it particularly suitable for the I/O port of high-frequency or high-speed IC.
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Citations
26 Claims
- 1. An electrostatic discharge (ESD) protection circuit with low input capacitance, suitable for an I/O pad, comprising a plurality of diodes, stacked and coupled between a first power line and the I/O pad, wherein during normal operation, the diodes are reverse-biased, and, when an ESD event occurs between a second power line and the I/O pad, the diodes are forward-biased to conduct ESD current.
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18. A power-rail ESD clamp circuit, suitable for an integrated circuit, coupled between two power lines, comprising:
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a substrate-triggered MOS, including;
a gate;
two source/drains, respectively coupled to two power lines; and
a substrate; and
an ESD detection circuit, providing a bias current to the substrate of the MOS, and a bias voltage to the gate of the MOS element to trigger the MOS and conduct ESD current when an ESD event occurs.
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Specification