Direct memory access controller for converting a transfer mode flexibly in accordance with a data transfer counter value
First Claim
1. A direct memory access controller (DMA) for converting a DMA transfer operation mode in accordance with a data transfer counter value, wherein the direct memory access controller performs data transfer operations between a memory and an input/output device without control operation by a central processing unit (CPU), comprising:
- a system bus interface for interfacing the CPU with an address of the input/output device, an address for writing/reading data from the memory, the transfer counter value of data to be written in/read out therefrom, and a control signal for a DMA transfer operation;
a first register for storing said address of the input/output device;
a second register for storing said initial address for writing/reading data from the memory;
a third register for storing said data transfer counter value;
a fourth register for storing said control signal;
a register control circuit for loading the addresses, the data transfer counter value, and the control signal from said system bus interface on a proper position of the first to fourth registers; and
a burst/single mode control circuit for receiving said data transfer counter value and said control signal from the third and fourth registers, for automatically converting the DMA transfer operation mode between a burst mode or a single mode, and performing the DMA transfer operation in accordance with the converted DMA transfer operation mode.
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Accused Products
Abstract
A DMA controller includes a burst/single mode control circuit for automatically converting a DMA transfer operation mode to a burst mode and/or a single mode regardless of a data transfer counter value, and for performing the DMA transfer operation. The burst/single mode control circuit carries out the burst mode DMA transfer operation without the need for a control operation of the CPU a number of times corresponding to a quotient which is the result that the data transfer counter value divided by the burst length, and carries out successively the single mode DMA transfer operation by the number of times corresponding to the remainder of the division.
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Citations
8 Claims
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1. A direct memory access controller (DMA) for converting a DMA transfer operation mode in accordance with a data transfer counter value, wherein the direct memory access controller performs data transfer operations between a memory and an input/output device without control operation by a central processing unit (CPU), comprising:
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a system bus interface for interfacing the CPU with an address of the input/output device, an address for writing/reading data from the memory, the transfer counter value of data to be written in/read out therefrom, and a control signal for a DMA transfer operation;
a first register for storing said address of the input/output device;
a second register for storing said initial address for writing/reading data from the memory;
a third register for storing said data transfer counter value;
a fourth register for storing said control signal;
a register control circuit for loading the addresses, the data transfer counter value, and the control signal from said system bus interface on a proper position of the first to fourth registers; and
a burst/single mode control circuit for receiving said data transfer counter value and said control signal from the third and fourth registers, for automatically converting the DMA transfer operation mode between a burst mode or a single mode, and performing the DMA transfer operation in accordance with the converted DMA transfer operation mode. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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Specification