On-chip method and apparatus for testing semiconductor circuits

• US 20020133771A1
• Filed: 03/16/2001
• Published: 09/19/2002
• Est. Priority Date: 03/16/2001
• Status: Active Grant

• Current Assignee: Silicon Storage Technology Incorporated (Microchip Technology Incorporated)
• Original Assignee: Advanced Technology Materials, Inc. (Entegris Incorporated)
• Inventors: Barnett, Philip C.
• Granted Patent: US 6,988,231 B2
• Time in Patent Office: Days
• US Class Current: 714/724
• CPC Class Codes: G01R 31/3187 Built-in tests
• CPC Class Codes: G06F 11/2635 using a storage for the test inputs, e.g. test ROM, script files

Abstract

A semiconductor circuit is disclosed that contains test hardware or test software (or both) that allows test functions to be executed directly from the memory of the semiconductor circuit. A remote testing station can issue a command indicating a specific test function that should be implemented. The disclosed semiconductor circuit independently performs the indicated test and provides the results to the test station. For an exemplary memory test, the test hardware and test software are employed to initially clear the memory and thereafter selectively apply a pattern to memory and read the applied pattern from each address to confirm that the correct pattern has been stored. The testing technique of the present invention reduces the number of pins that must be contacted by the tester, such as the address pins. In addition, the reduced number of contact points allows a number of semiconductor circuits to be setup and tested in parallel using the same automated test equipment (ATE).

Claims