Method and apparatus for integrated circuit debugging

• US 20020133794A1
• Filed: 02/20/2002
• Published: 09/19/2002
• Est. Priority Date: 02/24/2001
• Status: Abandoned Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Ganapathy, Kumar, Kanapathippillai, Ruban, Moussa, George
• Application Number:
  US10/081,331
• Publication Number:
  US 20020133794A1
• Time in Patent Office: Days
• US Class Current: 716/4
• CPC Class Codes: G01R 31/31705 Debugging aspects, e.g. using test circuits for debugging, using dedicated debugging test circuits generation of test sequences therefor G01R31/31835, using scan test therefor G01R31/318544
• CPC Class Codes: G01R 31/318558 Addressing or selecting of subparts of the device under test
• CPC Class Codes: G01R 31/318561 Identification of the subpart

Abstract

Method and apparatus for integrated circuit debugging. Three debug access methods into an integrated circuit are provided to control the testing and debugging of program code, functional blocks and circuitry therein. The debug access includes a serial access, an I/O mapped parallel access, and a direct parallel access. The three debug accesses have varying levels of intrusiveness and test/debug efficiency. Depending upon whether the integrated circuit is unpackaged, packaged, coupled to a printed circuit board or found within a system, any one or more of the three debug accesses to debugging the integrated circuit can be utilized.

Claims

1. A method comprising:

selecting one or more of three access methods provided in an integrated circuit to debug program code and/or circuitry contained therein, the three access methods including,

a serial debug access through a serial I/O test port of the integrated circuit,

a parallel I/O mapped debug access through a host I/O port of the integrated circuit, and

a parallel direct debug access through I/O pads of the integrated circuit.

2. The method of claim 1, wherein

the selecting of the one or more three access methods includes

setting a test mode input on an I/O pad of the integrated circuit.

3. The method of claim 1, wherein

the parallel direct debug access is through host I/O pads around circuitry of the host I/O port.

4. The method of claim 1, further comprising:

debugging the integrated circuit using test/debug instructions and data.

5. The method of claim 4, wherein

the debugging of the integrated circuit includes

setting a plurality of registers in the integrated circuit to control the debugging of the integrated circuit.

6. The method of claim 5, wherein

the plurality of registers in the integrated circuit control a debug controller in the integrated circuit to control the debugging.

7. The method of claim 5, wherein

the serial debug access method is selected and the setting of the plurality of registers is serially performed.

8. The method of claim 5, wherein

the parallel I/O mapped debug access method is selected and the setting of the plurality of registers is performed in parallel by memory map addressing of the plurality of registers and the data therein.

9. The method of claim 5, wherein

the parallel direct debug access method is selected and the setting of the plurality of registers is performed in parallel directly addressing each of the plurality of registers and the data therein.

10. The method of claim 2, wherein

the setting of the test mode input controls a select input control of a multiplexer in the integrated circuit to select between parallel I/O mapped debug access and parallel direct debug access to debug the integrated circuit.

11. An integrated circuit comprising:

debug registers to control on-chip testing and debugging of the integrated circuit;

a serial test port to access the debug registers serially;

a host I/O port to access the debug registers in parallel using I/O memory mapped access; and

I/O pads to access the debug registers in parallel using direct access.

12. The integrated circuit of claim 11, further comprising:

a multiplexer to select between loading the debug registers in parallel with the host I/O port and the I/O pads.

13. The integrated circuit of claim 12, wherein

the multiplexer is responsive to a test mode input of an I/O pad.

14. The integrated circuit of claim 11, further comprising:

a demultiplexer to select between reading information from the debug registers in parallel with the host I/O port and the I/O pads.

15. The integrated circuit of claim 14, wherein

the demultiplexer is responsive to a test mode input of an I/O pad.

16. The integrated circuit of claim 11, further comprising:

one or more digital signal processing units to test and debug.

17. The integrated circuit of claim 11, further comprising:

one or more functional blocks having circuitry to test and debug.

18. The integrated circuit of claim 11, further comprising:

one or more memories having program code to test and debug.

19. The integrated circuit of claim 11, further comprising:

a global memory having program code to test and debug.

20. The integrated circuit of claim 11, further comprising:

a debug controller coupled to the debug registers, the debug controller to test and debug circuitry within the integrated circuit in response to the information stored in the debug registers.

21. The integrated circuit of claim 20, wherein

the information stored in the debug registers is one or more debug instructions of the set of break execution, inject command, single step, reset, break at address, and PRAM.

22. A integrated circuit test system comprising:

an integrated circuit including,

debug registers to control on-chip testing and debugging of the integrated circuit,

a serial test port to load the debug registers serially,

a host I/O port to load the debug registers in parallel using I/O memory mapped access, and

I/O pads to load the debug registers in parallel using direct access; and

a tester including,

a processor readable storage medium, and

code recorded in the processor readable storage medium

to test and debug the integrated circuit,

to interface the tester to the serial test port of the integrated circuit to load the debug registers serially,

to interface the tester to the host I/O port of the integrated circuit to load the debug registers in parallel using I/O memory mapped access, and

to interface the tester to the I/O pads of the integrated circuit to load the debug registers in parallel using direct access.

23. The integrated circuit test system of claim 22, wherein

the processor readable storage medium is one or more of the set of magnetic storage medium, optical storage medium, or semiconductor storage medium.

24. The integrated circuit test system of claim 22, wherein the integrated circuit further includes

a multiplexer to select between loading the debug registers in parallel with the host I/O port and the I/O pads.

25. The integrated circuit test system of claim 24, wherein

the multiplexer is responsive to a test mode input of an I/O pad.

26. The integrated circuit test system of claim 22, wherein

the integrated circuit is a packaged integrated circuit and the tester is a packaged integrated circuit tester to test and debug the packaged integrated circuit.

27. The integrated circuit test system of claim 22, wherein

the integrated circuit is packaged and coupled to a printed circuit board and the tester is a printed circuit board tester to test and debug the printed circuit board including the integrated circuit.

28. The integrated circuit test system of claim 22, wherein

the integrated circuit is packaged and coupled to a printed circuit board which is inserted into a system and the tester is a system tester to test and debug the system and the printed circuit board including the integrated circuit.