Method and apparatus for integrated circuit debugging
First Claim
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1. A method comprising:
- selecting one or more of three access methods provided in an integrated circuit to debug program code and/or circuitry contained therein, the three access methods including, a serial debug access through a serial I/O test port of the integrated circuit, a parallel I/O mapped debug access through a host I/O port of the integrated circuit, and a parallel direct debug access through I/O pads of the integrated circuit.
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Abstract
Method and apparatus for integrated circuit debugging. Three debug access methods into an integrated circuit are provided to control the testing and debugging of program code, functional blocks and circuitry therein. The debug access includes a serial access, an I/O mapped parallel access, and a direct parallel access. The three debug accesses have varying levels of intrusiveness and test/debug efficiency. Depending upon whether the integrated circuit is unpackaged, packaged, coupled to a printed circuit board or found within a system, any one or more of the three debug accesses to debugging the integrated circuit can be utilized.
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Citations
28 Claims
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1. A method comprising:
selecting one or more of three access methods provided in an integrated circuit to debug program code and/or circuitry contained therein, the three access methods including, a serial debug access through a serial I/O test port of the integrated circuit, a parallel I/O mapped debug access through a host I/O port of the integrated circuit, and a parallel direct debug access through I/O pads of the integrated circuit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. An integrated circuit comprising:
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debug registers to control on-chip testing and debugging of the integrated circuit;
a serial test port to access the debug registers serially;
a host I/O port to access the debug registers in parallel using I/O memory mapped access; and
I/O pads to access the debug registers in parallel using direct access. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20, 21)
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22. A integrated circuit test system comprising:
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an integrated circuit including, debug registers to control on-chip testing and debugging of the integrated circuit, a serial test port to load the debug registers serially, a host I/O port to load the debug registers in parallel using I/O memory mapped access, and I/O pads to load the debug registers in parallel using direct access; and
a tester including, a processor readable storage medium, and code recorded in the processor readable storage medium to test and debug the integrated circuit, to interface the tester to the serial test port of the integrated circuit to load the debug registers serially, to interface the tester to the host I/O port of the integrated circuit to load the debug registers in parallel using I/O memory mapped access, and to interface the tester to the I/O pads of the integrated circuit to load the debug registers in parallel using direct access. - View Dependent Claims (23, 24, 25, 26, 27, 28)
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Specification