Trace-pad interface for improved signal quality

• US 20020134576A1
• Filed: 12/19/2000
• Published: 09/26/2002
• Est. Priority Date: 10/16/1997
• Status: Active Grant

• Current Assignee: Ignatius T. Chong, Jacqueline V. Csonka
• Original Assignee: Ignatius T. Chong, Jacqueline V. Csonka
• Inventors: Csonka, Jacqueline V., Chong, Ignatius T.
• Granted Patent: US 7,269,028 B2
• Time in Patent Office: Days
• US Class Current: 174/250
• CPC Class Codes: H05K 1/0216 Reduction of cross-talk, noise or electromagnetic interference grounding H05K1/0215
• CPC Class Codes: H05K 1/111 Pads for surface mounting, e.g. lay-out
• CPC Class Codes: H05K 2201/09281 Layout details of a single conductor meander H05K2201/09263; layout details of angles or corners H05K2201/09272
• CPC Class Codes: H05K 2201/10689 Leaded Integrated Circuit [IC] package, e.g. dual-in-line [DIL]
• CPC Class Codes: Y02P 70/50 Manufacturing or production processes characterised by the final manufactured product

Abstract

A method of routing or laying out signal traces on printed wire or circuit board in order to improve signal transmission quality. The method includes routing a given signal trace such that it is electrically connected to a rectangular corner of a substantially wider component pin pad and forms an angle of approximately 135 degrees with the proximate sides of the pad, thereby minimizing the impedance discontinuity at the interface or junction of the signal trace and pad and hence minimizing the reflection of the digital signal at the interface or junction.

Claims

1. A circuit substrate associated with a signal-triggered digital circuit, the circuit substrate comprising:

a conducting interface for electrical connection to an input receiver, the input receiver receiving digital signals over said digital circuit and being responsive to triggering induced by said digital signals;

a conducting signal path, the conducting signal path being connected to said conducting interface, the signal path carrying said digital signals thereover; and

wherein the conducting interface is substantially rectangular in planar view and the conducting path connected thereto as aforesaid has a longitudinal centerline axis which forms an angle in a range of 110 to 160 degrees with respect to a side of the conducting interface to which the path is connected to thereby produce a reduced reflection of said digital signals at the connection between said conducting interface and said conducting path when compared to a connection wherein said angle has a value of 90 degrees.

2. The circuit substrate according to claim 1, wherein the conducting signal path is connected to the conducting interface at a corner thereof.

3. The circuit substrate according to claim 2, wherein the conducting signal path has a length which is at least ⅙

th of a transition electrical length of the digital signal carried thereover, the transitional electrical length constituting a transient time of the said digital signal multiplied by a propagation speed of the said digital signal over said conducting signal path, and wherein the transient time of the said digital signal is selected from the group comprising a rise time thereof and a fall time thereof.

4. The circuit substrate according to claim 3, wherein the conducting signal path has a length which is at least said transition electrical length of the digital signal carried thereover.

5. The circuit substrate according to claim 2, wherein said angle in a range of 110 to 160 degrees is an angle of 135 degrees.

6. The circuit substrate according to claim 5, wherein the circuit substrate is a printed circuit board, the conducting interface is a pad and the conducting signal path is a trace.

7. The circuit substrate according to claim 6, wherein the pad is substantially square in planar view and the trace has a width which is ⅕

th of a width of a side of the pad to which the trace is connected.

8. The circuit substrate according to claim 6, wherein when the input receiver is mounted to the pad, the trace has a thickness which is in a range of ⅕

th to ⅙

th of a thickness of the pad to which the trace is connected.

9. The circuit substrate according to claim 6, wherein when the input receiver is mounted to the pad, the pad has a width of 22 mils and a thickness in a range of 6 mils to 7 mils, and wherein the trace has a width of 4 mils and a thickness of 1.2 mils.

10. The circuit substrate according to claim 6, wherein the input receiver is comprised in a memory module and the trace carries digital signals in the form of control signals generated by a memory controller.

11. The circuit substrate according to claim 10, wherein the memory module is a dual in-line memory module (DIMM) connected to the pad by a slot which accepts an edge connector of said module.