Seed layer processes

• US 20020134684A1
• Filed: 10/25/2001
• Published: 09/26/2002
• Est. Priority Date: 10/25/2000
• Status: Abandoned Application

• Current Assignee: Shipley Company, LLC (Dow, Inc.)
• Original Assignee: Shipley Company, LLC (Dow, Inc.)
• Inventors: Calvert, Jeffrey M., Morrissey, Denis, Merricks, David
• Application Number:
  US10/001,683
• Publication Number:
  US 20020134684A1
• Time in Patent Office: Days
• US Class Current: 205/118
• CPC Class Codes: C25D 7/123 Semiconductors first coated with a seed layer or a conductive layer
• CPC Class Codes: H01L 21/288 from a liquid, e.g. electrolytic deposition
• CPC Class Codes: H01L 21/2885 using an external electrical current, i.e. electro-deposition
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76861 Post-treatment or after-treatment not introducing additional chemical elements into the layer
• CPC Class Codes: H01L 21/76868 Forming or treating discontinuous thin films, e.g. repair, enhancement or reinforcement of discontinuous thin films
• CPC Class Codes: H01L 21/76873 for electroplating
• CPC Class Codes: H01L 2221/1089 Stacks of seed layers
• CPC Class Codes: H05K 3/423 characterised by electroplating method

Abstract

Disclosed is a process flows for treating seed layers including copper such that various problems such as oxidation and insufficient coverage can be repaired in an effective and efficient manner.

Claims

1. A method for electroplating a plurality of electronic devices, each electronic device having apertures and comprising a copper containing seed layer comprising, comprising the steps of:

a) electroplating a layer of metal on the seed layer of a first electronic device to at least substantially fill the apertures;

b) testing the first electronic device for voids in the apertures;

c) if no voids exist in step b), electroplating a layer of metal on the seed layer of the remaining electronic devices;

d) if voids exist in step b), subjecting a second electronic device to a seed layer repair process selected from cathodic activation or lateral growth enhancement, followed by electroplating a layer of metal on the seed layer of the second electronic device to at least substantially fill the apertures;

e) testing the second electronic device for voids in the apertures;

f) if no voids exist in step e), electroplating a metal layer on the seed layer of the remaining electronic devices following the process of step d);

g) if voids exist in step e), subjecting a third electronic device to a seed layer repair process selected from cathodic activation or lateral growth enhancement, followed by electroplating a layer of metal on the seed layer of the third electronic device to at least substantially fill the apertures, provided that the seed layer repair process is different from the seed layer repair process of step d);

h) testing the third electronic device for voids in the apertures;

i) if no voids exist in step h), electroplating a metal layer on the seed layer of the remaining electronic devices following the process of step g);

j) if voids exist in step h), subjecting the remaining electronic devices to a seed layer repair process selected from cathodic activation plus lateral growth enhancement or cathodic activation plus solution seed layer deposition, followed by electroplating a metal layer on the seed layer of the remaining electronic devices.

2. The method of claim 1 wherein the seed layer is a copper alloy.

3. The method of claim 1 wherein the plurality of electronic devices is a plurality of wafers.

4. The method of claim 1 wherein each of the electronic devices further comprises a barrier layer.

5. The method of claim 4 wherein the barrier layer is selected from tantalum, tantalum nitride, titanium, titanium nitride, tungsten, tungsten nitride, molybdenum, molybdenum nitride, cobalt, cobalt nitride.

6. The method of claim 1 wherein the apertures have a width ≦

1 μ

m.

7. The method of claim 1 wherein the apertures have an aspect ratio of from 1:

1 to 10;

1.

8. A method for electroplating a plurality of electronic devices, each electronic device having apertures and comprising a copper containing seed layer comprising the steps of:

a) subjecting a first electronic device to a cathodic activation step;

b) electroplating a layer of metal on the seed layer of the first electronic device to at least substantially fill the apertures;

c) testing the first electronic device for voids in the apertures;

d) if no voids exist in step c), subjecting the remaining electronic devices to a cathodic activation step followed by electroplating a layer of metal on the seed layer of the remaining electronic devices;

e) if voids exist in step c), subjecting the remaining wafers to a cathodic activation step plus a seed layer repair process selected from lateral growth enhancement or solution seed layer deposition followed by electroplating a layer of metal on the seed layer of the remaining electronic devices.

9. The method of claim 8 wherein the plurality of electronic devices is a plurality of wafers.

10. The method of claim 8 wherein each of the electronic devices further comprises a barrier layer.

11. The method of claim 10 wherein the barrier layer is selected from tantalum, tantalum nitride, titanium, titanium nitride, tungsten, tungsten nitride, molybdenum, molybdenum nitride, cobalt, cobalt nitride.

12. the method of claim 8 wherein the apertures have a width ≦

1 μ

m.

13. The method of claim 8 wherein the apertures have an aspect ratio of from 1:

1 to 10;

1.

15. The method of claim 14 wherein the plurality of electronic devices is a plurality of wafers.

16. The method of claim 14 wherein each of the electronic devices further comprises a barrier layer.

17. The method of claim 14 wherein the apertures have a width ≦

1 μ

m.

18. The method of claim 14 wherein the apertures have an aspect ratio of from 1:

1 to 10;

1.

14. A method for manufacturing a plurality of electronic devices, each electronic device having apertures and comprising a copper containing seed layer, comprising the steps of:

a) electroplating a layer of metal on the seed layer of a first electronic device to at least substantially fill the apertures;

b) testing the first electronic device for voids in the apertures;

c) if no voids exist in step b), electroplating a layer of metal on the seed layer of the remaining electronic devices;

d) if voids exist in step b), subjecting a second electronic device to a seed layer repair process selected from cathodic activation or lateral growth enhancement, followed by electroplating a layer of metal on the seed layer of the second electronic device to at least substantially fill the apertures;

e) testing the second electronic device for voids in the apertures;

f) if no voids exist in step e), electroplating a metal layer on the seed layer of the remaining electronic devices following the process of step d);

g) if voids exist in step e), subjecting a third electronic device to a seed layer repair process selected from cathodic activation or lateral growth enhancement, followed by electroplating a layer of metal on the seed layer of the third electronic device to at least substantially fill the apertures, provided that the seed layer repair process is different from the seed layer repair process of step d);

h) testing the third electronic device for voids in the apertures;

i) if no voids exist in step g), electroplating a metal layer on the seed layer of the remaining electronic devices following the process of step g);

j) if voids exist in step g), subjecting the remaining electronic devices to a seed layer repair process selected from cathodic activation plus lateral growth enhancement or cathodic activation plus solution seed layer deposition, followed by electroplating a metal layer on the seed layer of the remaining electronic devices.

19. A method for manufacturing a plurality of electronic devices, each electronic device having apertures and comprising a copper containing seed layer, comprising the steps of:

a) subjecting a first electronic device to a cathodic activation step;

b) electroplating a layer of metal on the seed layer of the first electronic device to at least substantially fill the apertures;

c) testing the first electronic device for voids in the apertures;

d) if no voids exist in step c), subjecting the remaining electronic devices to a cathodic activation step followed by electroplating a layer of metal on the seed layer of the remaining electronic devices;

e) if voids exist in step c), subjecting the remaining wafers to a cathodic activation step plus a seed layer repair process selected from lateral growth enhancement or solution seed layer deposition followed by electroplating a layer of metal on the seed layer of the remaining electronic devices.