Bond wire tuning of RF power transistors and amplifiers

• US 20020134993A1
• Filed: 03/20/2001
• Published: 09/26/2002
• Est. Priority Date: 03/20/2001
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Ericsson, Inc. (Telefonaktiebolaget LM Ericsson)
• Inventors: Moller, Tom, Perugupalli, Prasanth, Dixit, Nagaraj V., Leighton, Larry
• Granted Patent: US 6,806,106 B2
• Time in Patent Office: Days
• US Class Current: 257/177
• CPC Class Codes: H01L 2223/6644 Packaging aspects of high-frequency amplifiers
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/49111 the connectors connecting two common bonding areas, e.g. Litz or braid wires
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 23/64 Impedance arrangements
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01014 Silicon [Si]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/01083 Bismuth [Bi]
• CPC Class Codes: H01L 2924/01322 Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/10253 Silicon [Si]
• CPC Class Codes: H01L 2924/12042 LASER
• CPC Class Codes: H01L 2924/19041 being a capacitor
• CPC Class Codes: H01L 2924/19042 being an inductor
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/30111 : matching
• CPC Class Codes: H03F 1/565 : using inductive elements
• CPC Class Codes: H03F 3/191 : Tuned amplifiers H03F3/193, H03F3/195 take precedence

Abstract

A method for manufacturing a power transistor circuit includes securing a die to a substrate, the die comprising a transistor having an input terminal and an output terminal. One or more performance characteristics of the transistor are measured. Using one or more wire sets, the transistor input terminal is electrically connected to one or more input matching elements and an input signal lead. The impedance of the one or more wire sets, (as determined by selecting a desired number and/or length of the wires in each set, is selected based at least in part on the measured transistor performance characteristic(s). Similarly, using one or more additional wire sets, the transistor output terminal is electrically connected to one or more output matching elements and an output signal lead, wherein the impedance of the additional wire sets is selected based at least in part on the measured transistor performance characteristic(s).

Claims

1. A method of manufacturing a power transistor circuit, comprising:

securing a die to a substrate, the die comprising a transistor having an input terminal;

measuring a performance characteristic of the transistor;

using one or more wires to electrically couple the transistor input terminal to an input matching element, an input signal lead, or both; and

setting the impedance of the one or more wires based at least in part on the measured transistor performance characteristic.

2. The method of claim 1, wherein the performance characteristic is defined, at least in part, by one or more of input capacitance, impedance, gain flatness, and signal phase shift.

3. The method of claim 1, wherein the impedance of the one or more wires is set by selecting a number of wires used to make at least one electrical connection of the transistor circuit.

4. The method of claim 1, wherein the impedance of the one or more wires is set by selecting a length of at least one wire used to make at least one electrical connection of the transistor circuit.

5. A method of manufacturing a power transistor circuit, comprising:

securing a die to a substrate, the die comprising a transistor having an output terminal;

measuring a performance characteristic of the transistor;

using one or more wires to electrically couple the transistor output terminal to an output matching element, an output signal lead, or both; and

setting the impedance of the one or more wires based at least in part on the measured transistor performance characteristic.

6. The method of claim 5, wherein the performance characteristic is defined, at least in part, by one or more of output capacitance impedance, gain flatness, and signal phase shift.

7. The method of claim 5, wherein the impedance of the one or more wires is set by selecting a number of wires used to make at least one electrical connection of the transistor circuit.

8. The method of claim 5, wherein the impedance of the one or more wires is set by selecting a length of at least one wire used to make at least one electrical connection of the transistor circuit.

9. A power transistor circuit, comprising:

a substrate;

a die secured to the substrate, the die comprising a transistor having an input terminal;

one or both of an input lead and an input matching element secured to the substrate; and

one or more wires electrically coupling the transistor input terminal to the one or both of the input matching element and input signal lead, wherein the impedance of the one or more wires is based at least in part on a performance characteristic of the transistor measured after the die is secured to the substrate.

10. The circuit of claim 9, wherein the performance characteristic is defined, at least in part, by one or more of input capacitance, impedance, gain flatness, and signal phase shift.

11. The circuit of claim 9, wherein the impedance of the one or more wires is determined by selecting a number of wires used to make at least one electrical connection of the transistor circuit.

12. The circuit of claim 9, wherein the impedance of the one or more wires is determined by selecting a length of at least one wire used to make at least one electrical connection of the transistor circuit.

14. The circuit of claim 13, wherein the performance characteristic is defined, at least in part, by one or more of output capacitance, impedance, gain flatness, and signal phase shift.

15. The circuit of claim 13, wherein the impedance of the one or more wires is determined by selecting a number of wires used to make at least one electrical connection of the transistor circuit.

16. The circuit of claim 13, wherein the impedance of the one or more wires is determined by selecting a length of at least one wire used to make at least one electrical connection of the transistor circuit.

13. A power transistor circuit, comprising:

a substrate;

a die secured to the substrate, the die comprising a transistor having an output terminal;

one or both of an output lead and an output matching element secured to the substrate; and

one or more wires electrically coupling the transistor output terminal to the one or both of the output matching element and output signal lead, wherein the impedance of the one or more wires is based at least in part on a performance characteristic of the transistor measured after the die is secured to the substrate.