Thin planar semiconductor device having electrodes on both surfaces and method of fabricating same

• US 20020135057A1
• Filed: 03/19/2002
• Published: 09/26/2002
• Est. Priority Date: 03/26/2001
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Inventors: Kurita, Yoichiro
• Granted Patent: US 7,034,386 B2
• Time in Patent Office: Days
• US Class Current: 257/685
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/81005 being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/0652 Bump or bump-like direct electrical connections from substrate to substrate
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 2225/06572 Auxiliary carrier between devices, the carrier having an electrical connection structure
• CPC Class Codes: H01L 2225/06582 Housing for the assembly, e.g. chip scale package [CSP]
• CPC Class Codes: H01L 2225/06586 Housing with external bump or bump-like connectors
• CPC Class Codes: H01L 2225/1035 the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15331 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/18161 of a flip chip

Abstract

A thin, planar semiconductor device having electrodes on both surfaces is disclosed. This semiconductor device is provided with an IC chip and a wiring layer having one side that is electrically connected to surface electrodes of the IC chip. On this surface of the wiring layer, conductive posts are provided on wiring of the wiring layer, and an insulating resin covers all portions not occupied by the IC chip and conductive posts. The end surfaces of the conductive posts are exposed from the insulating resin and are used as first planar electrodes. In addition, a resist layer is formed on the opposite surface of the wiring layer. Exposed portions are formed in the resist layer to expose desired wiring portions of the wiring layer. These exposed portions are used as second planar electrodes. Stacking semiconductor devices of this construction enables an improvement in the integration of semiconductor integrated circuits.

Claims

1. A semiconductor device comprising:

an IC chip;

a wiring layer that is a planar wiring layer constituted by electrical wiring, surface electrodes of said IC chip being electrically connected to a first surface of said wiring layer;

conductive posts provided on wiring of said wiring layer on said first surface of said wiring layer;

insulating resin covering portions not occupied by said IC chip and conductive posts on said first surface of said wiring layer;

end surfaces of said conductive posts exposed from said resin;

a resist layer formed on a second surface of said wiring layer that is the opposite surface of said wiring layer; and

exposed portions provided in said resist layer in which desired wiring portions of said wiring layer are exposed.

2. A semiconductor device according to claim 1, wherein first electrode terminals are formed on end surfaces of conductive posts, and second electrode terminals are formed on wiring of exposed portions.

3. A semiconductor device according to claim 2, wherein at least one of first electrode terminals and second electrode terminals are ball-shaped solder.

4. An assembly of semiconductor devices in which a plurality of semiconductor devices according to claim 1 are stacked, wherein, among the stacked semiconductor devices, exposed portions of wiring layer of one semiconductor device are electrically connected to end surfaces of conductive posts of another semiconductor device.

5. A semiconductor device according to claim 1, said semiconductor device further comprising a planar wiring layer that includes wiring that is electrically connected to end surfaces of conductive posts.

6. A semiconductor device according to claim 5, wherein first electrode terminals are formed on wiring of the planar wiring layer that includes wiring that is electrically connected to end surfaces of conductive posts, and second electrode terminals are formed on wiring of exposed portions.

7. A method of fabricating a semiconductor device, comprising the steps of:

preparing a wiring substrate that is constituted by a base material and a wiring layer that is composed of wiring that is formed on this base material, and an IC chip having electrode terminals formed on its surface;

providing conductive posts on desired wiring of said wiring layer of said wiring substrate;

connecting surface electrodes of said IC chip to desired wiring of said wiring layer of said wiring substrate;

covering said IC chip and said conductive posts that have been arranged on the surface of said wiring layer of said wiring substrate with an insulating resin;

removing said base material from said wiring substrate to expose said wiring layer;

forming a resist layer on the exposed wiring layer with the exception of desired wiring portions; and

grinding away said insulating resin to expose said end surfaces of said conductive posts.

8. A method of fabricating a semiconductor device according to claim 7, further comprising a step of forming first electrode terminals on end surfaces of conductive posts and forming second electrode terminals on desired wiring portions of wiring layer that are not covered by resist layer.

9. A method of fabricating an assembly of semiconductor devices in which a plurality of semiconductor devices that have been fabricated by the method of fabricating a semiconductor device according to claim 7 are stacked, wherein among the stacked semiconductor devices, exposed portions of wiring layer of one semiconductor device are electrically connected to end surfaces of conductive posts of another semiconductor device.