High speed voltage mode differential digital output driver with edge-emphasis and pre-equalization

• US 20020135404A1
• Filed: 03/14/2002
• Published: 09/26/2002
• Est. Priority Date: 03/21/2001
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Payne, Robert F., Palermo, Samuel M., Chan, Chung San Roger
• Granted Patent: US 6,624,670 B2
• Time in Patent Office: Days
• US Class Current: 327/108
• CPC Class Codes: H03K 19/01721 by means of a pull-up or down element
• CPC Class Codes: H03K 19/018521 of complementary type, e.g. CMOS
• CPC Class Codes: H04L 25/0272 Arrangements for coupling to multiple lines, e.g. for differential transmission
• CPC Class Codes: H04L 25/028 Arrangements specific to the transmitter end
• CPC Class Codes: H04L 25/03878 Line equalisers; line build-out devices

Abstract

The differential driver consists of two feedback loops 20 and 22, and two inverter pairs 24 and 26. The two feedback loops 20 and 22 regulate the source voltages for the two inverter pairs 24 and 26 to the reference voltages V_REFHI and V_REFLO. The two inverter pairs 24 and 26 switch the output load RL and CL between the two regulated voltages in response to the input voltages IN and IN−. The reference voltages V_REFHI and V_REFLO are created by a reference cell and set the output high and low voltages.

Claims

1. A differential output driver comprising:

a first inverter having a positive input node and a negative output node, the first inverter is coupled to a positive power supply node and a negative power supply node;

a second inverter having a negative input node and a positive output node, the second inverter is coupled to the positive power supply node and the negative power supply node;

a first feedback loop for regulating the positive power supply node; and

a second feedback loop for regulating the negative power supply node.

2. The circuit of claim 1 wherein the first feedback loop comprises:

a first transistor coupled between a first voltage supply node and the positive power supply node;

a first amplifier having an output coupled to a control node of the first transistor;

a first input of the first amplifier coupled to the positive power supply node; and

a second input of the first amplifier coupled to a first reference node.

3. The circuit of claim 2 wherein the second feedback loop comprises:

a second transistor coupled between a second voltage supply node and the negative power supply node;

a second amplifier having an output coupled to a control node of the second transistor;

a first input of the second amplifier coupled to the negative power supply node; and

a second input of the second amplifier coupled to a second reference node.

4. The circuit of claim 3 further comprising a reference circuit coupled to the first and second reference nodes.

5. The circuit of claim 4 wherein the reference circuit comprises:

a first transistor coupled to the first reference node;

a first resistor coupled between the first reference node and the first voltage supply node;

a second transistor coupled to the second reference node;

a second resistor coupled between the first and second transistors; and

a third resistor coupled between the second reference node and the second voltage supply node.

6. The circuit of claim 1 further comprising:

a first edge emphasis circuit coupled to the positive output node; and

a second edge emphasis circuit coupled to the negative output node.

7. The circuit of claim 6 wherein the first edge emphasis circuit comprises:

an active pull-up coupled to the positive output node; and

an active pull-down coupled to the positive output node.

8. The circuit of claim 6 wherein the second edge emphasis circuit comprises:

an active pull-up coupled to the negative output node; and

an active pull-down coupled to the negative output node.

9. A differential driver comprising:

a first inverter for driving a positive differential output;

a second inverter for driving a negative differential output;

a first feedback loop for regulating a first power supply for the first and second inverters;

a second feedback loop for regulating a second power supply for the first and second inverters;

a reference circuit for providing a first reference voltage to the first feedback loop and a second reference voltage to the second feedback loop.

10. The circuit of claim 9 wherein the first feedback loop comprises:

a first transistor coupled between a first voltage supply node and first power supply nodes for the first and second inverters;

a first amplifier having an output coupled to a control node of the first transistor;

a first input of the first amplifier coupled to the first power supply nodes; and

a second input of the first amplifier coupled to a first reference node.

11. The circuit of claim 10 wherein the second feedback loop comprises:

a second transistor coupled between a second voltage supply node and second power supply nodes for the first and second inverters;

a second amplifier having an output coupled to a control node of the second transistor;

a first input of the second amplifier coupled to the second power supply nodes; and

a second input of the second amplifier coupled to a second reference node.

12. The circuit of claim 11 further comprising a reference circuit coupled to the first and second reference nodes.

13. The circuit of claim 12 wherein the reference circuit comprises:

a first transistor coupled to the first reference node;

a first resistor coupled between the first reference node and the first voltage supply node;

a second transistor coupled to the second reference node;

a second resistor coupled between the first and second transistors; and

a third resistor coupled between the second reference node and the second voltage supply node.

14. The circuit of claim 9 further comprising:

a first edge emphasis circuit coupled to the positive differential output; and

a second edge emphasis circuit coupled to the negative differential output.

15. The circuit of claim 14 wherein the first edge emphasis circuit comprises:

an active pull-up coupled to the positive differential output; and

an active pull-down coupled to the positive differential output.

16. The circuit of claim 14 wherein the second edge emphasis circuit comprises:

an active pull-up coupled to the negative differential output; and

an active pull-down coupled to the negative differential output.

17. A method for differentially driving a load comprising:

driving a first end of the load with a first inverter;

driving a second end of the load with s second inverter;

regulating a first power supply of the first and second inverters with a first feedback loop; and

regulating a second power supply of the first and second inverters with a second feedback loop.