Apparatus and method for phase lock loop gain control using unit current sources

• US 20020135428A1
• Filed: 03/20/2001
• Published: 09/26/2002
• Est. Priority Date: 03/20/2001
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Gomez, Ramon A.
• Granted Patent: US 6,583,675 B2
• Time in Patent Office: Days
• US Class Current: 331/17
• CPC Class Codes: H03B 2200/0046 including measures to switch the gain of an amplifier
• CPC Class Codes: H03B 2200/0048 including measures to switch the frequency band, e.g. by harmonic selection
• CPC Class Codes: H03B 2200/005 including measures to switch a capacitor
• CPC Class Codes: H03B 2201/02 Varying the frequency of the oscillations by electronic means
• CPC Class Codes: H03B 2201/0208 the means being an element with a variable capacitance, e.g. capacitance diode
• CPC Class Codes: H03B 2201/025 the means being an electronic switch for switching in or out oscillator elements
• CPC Class Codes: H03B 5/1212 the amplifier comprising a pair of transistors, wherein an output terminal of each being connected to an input terminal of the other, e.g. a cross coupled pair
• CPC Class Codes: H03B 5/1215 the current source or degeneration circuit being in common to both transistors of the pair, e.g. a cross-coupled long-tailed pair
• CPC Class Codes: H03B 5/1228 the amplifier comprising one or more field effect transistors
• CPC Class Codes: H03B 5/1243 the means comprising voltage variable capacitance diodes
• CPC Class Codes: H03B 5/1253 the transistors being field-effect transistors
• CPC Class Codes: H03B 5/1265 switched capacitors
• CPC Class Codes: H03B 5/1278 the parameter being an amplitude of a signal, e.g. maintaining a constant output amplitude over the frequency range
• CPC Class Codes: H03D 7/165 at least two frequency changers being located in different paths, e.g. in two paths with carriers in quadrature combined with amplitude demodulation H03D1/2245, combined with angle demodulation H03D3/007; N-path filters H03H19/002
• CPC Class Codes: H03D 7/18 Modifications of frequency-changers for eliminating image frequencies H03D7/16 takes precedence
• CPC Class Codes: H03J 2200/10 Tuning of a resonator by means of digitally controlled capacitor bank
• CPC Class Codes: H03J 5/244 using electronic means
• CPC Class Codes: H03L 7/00 Automatic control of frequency or phase; Synchronisation
• CPC Class Codes: H03L 7/0898 the source or sink current values being variable H03L7/0896 takes precedence
• CPC Class Codes: H03L 7/093 using special filtering or amplification characteristics in the loop H03L7/087 - H03L7/091 take precedence
• CPC Class Codes: H03L 7/099 : concerning mainly the controlled oscillator of the loop
• CPC Class Codes: H03L 7/1072 : by changing characteristics of the charge pump, e.g. changing the gain
• CPC Class Codes: H03L 7/18 : using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence

Abstract

A gain compensator compensates for the gain variation of a varactor-tuned voltage tuned oscillator (VCO) in a phase lock loop (PLL). The VCO includes a parallel LC circuit having multiple fixed capacitors that can be switched-in or switched-out of the LC circuit according to a capacitor control signal to perform band-select tuning of the VCO. The gain compensator compensates for the variable VCO gain by generating a charge pump reference current that is based on the same capacitor control signal that controls the fixed capacitors in the LC circuit. The gain compensator generates the charge pump reference current by replicating a reference scale current using unit current sources. The number of times the reference scale current is replicated is based on the fixed capacitance that is switched-in to the LC circuit and therefore the frequency band of the PLL. The reference scale current is generated based on a PLL control that specifics certain PLL characteristics such as reference frequency, loop bandwidth, and loop damping. Therefore, the reference pump current can be efficiently optimized for changing PLL operating conditions, in addition to compensating for variable VCO gain.

Claims

1. A gain compensator circuit that determines a reference pump current for a charge pump in a phase lock loop (PLL), comprising:

a plurality of unit current sources that are arranged into at least one group, said group responsive to a capacitor control signal and generating a portion of the reference pump current when said group is activated, wherein said capacitor control signal also controls a corresponding fixed capacitor; and

means for scaling said unit current sources responsive to a phase lock loop control signal.

2. The gain compensator circuit of claim 1, wherein a number of said unit current sources in said group corresponds to a capacitance of said corresponding fixed capacitor.

3. The gain compensator circuit of claim 1, wherein a number of said unit current sources in said group is determined so as to compensate for variable VCO gain that is caused by said fixed capacitor.

4. The gain compensator circuit of claim 1, wherein said fixed capacitor determines a resonant frequency of a resonant circuit.

5. The gain compensator circuit of claim 4, wherein said resonant frequency determines an oscillation frequency of a VCO.

6. The gain compensator circuit of claim 1, wherein said capacitor control signal switches-in said fixed capacitor and activates said group of said unit current sources.

7. The gain compensator circuit of claim 1, wherein said unit current sources replicate a reference scale current, wherein the number of times said reference scale current is replicated is based on a total fixed capacitance that is switched-in to a resonant circuit.

8. The gain compensator circuit of claim 7, wherein said means for scaling adjusts said reference scale current based on said PLL control signal.

9. The gain compensator circuit of claim 8, wherein said means for scaling comprises one or more weighted current sources that are responsive to said PLL control signal.

10. The gain compensator circuit of claim 9, wherein said PLL control signal indicates at least one of reference frequency, bandwidth, and damping factor of said PLL.

11. The gain compensator circuit of claim 1, wherein said means for scaling and said unit current sources form a current mirror.

12. The gain compensator circuit of claim 1, wherein each unit current source is a field effect transistor (FET) that is controlled by said means for scaling when said unit current sources are activated.

13. The gain compensator circuit of claim 12, wherein said means for scaling comprises a means for generating a gate voltage that is applied to a gate of said FETs when said group is activated.

14. The gain compensator circuit of claim 12, wherein said means for scaling comprises a means for generating a gate voltage based on said PLL control signal, and wherein said gain compensator circuit further comprises:

a switch that is connected to said group of unit current sources, wherein said switch applies said gate voltage to said group of unit current sources when said corresponding fixed capacitor is switched-in to a resonant circuit.

16. The gain compensator circuit of claim 15, wherein a number of said unit current sources in said group is determined based on a capacitance of said fixed capacitor that is controlled by said corresponding capacitor control signal.

17. The gain compensator circuit of claim 15, wherein a number of said unit current sources in said group is determined to compensate for variable VCO gain that occurs when said corresponding fixed capacitor is switched-in to said VCO tuning circuit.

18. The gain compensator circuit of claim 15, wherein each of said unit current sources is a field effect transistor (FET), and wherein said gate voltage is applied to said FETs by said switch according to said capacitor control signal.

19. The gain compensator circuit of claim 15, wherein each of said unit current sources is a field effect transistor (FET), and wherein said gate voltage is applied to said FETs when said corresponding fixed capacitor is switched-in to said VCO tuning circuit.

20. The gain compensator circuit of claim 15, wherein said voltage generator includes:

a current scaler that generates a reference scale current according to a PLL control signal; and

a means for generating said gate voltage based on said reference scale current.

21. The gain compensator circuit of claim 20, wherein said means for generating comprises a diode-connected FET that conducts said reference scale current, when said diode-connected FET generates said gate voltage to correspond to said reference scale current.

22. The gain compensator circuit of claim 20, wherein said current scaler includes one or more weighted current sources that are controlled by said PLL control signal, to produce said reference scale current based on said control signal.

24. The method of claim 23, further comprising the steps of:

(5) adjusting said reference scale current based on a PLL control signal that indicates characteristics of said PLL.

25. The method of claim 24, wherein step (5) comprises the step of adjusting one or more weighted current sources that generate said reference scale current based on said PLL control signal.

26. The method of claim 24, wherein said PLL characteristics include at least one of reference frequency, PLL bandwidth, and PLL damping factor.

28. The method of claim 27, wherein step (3) comprises the steps of activating said group of said unit current sources when said corresponding fixed capacitor is switched-in to said VCO tuning circuit by said corresponding capacitor signal.

29. The method of claim 27, wherein step (3) comprises the step of applying a gate voltage to said unit current sources when said corresponding fixed capacitor is switched into said VCO tuning circuit, wherein said gate voltage is based on said reference scale current.

30. The method of claim 27, wherein each of said unit current sources is a field effect transistor (FET), and wherein step (3) comprises the step of applying a gate voltage to a gate of said FETs when said group is activated.

31. The method of claim 27, further comprising the step of adjusting said reference scale current based on a PLL control signal, and thereby adjusting said reference pump current.

32. The method of claim 31, wherein said reference scale current is generated by one or more weighted current sources that are controlled by said PLL control signal, wherein said step of adjusting comprises the step of adjusting said one or more weighted current sources based on said PLL control signal.

33. The method of claim 27, further comprising the step of:

(6) de-activating said group of unit current sources based on said capacitor control signal.

34. The method of claim 27, further comprising the step of

(6) de-activating said group of unit current sources when said corresponding fixed capacitor is switched-out of said VCO tuning circuit by said capacitor control signal.

35. The method of claim 34, wherein each of said unit current sources is a field effect transistor (FET), and wherein said step of de-activating comprises the step of cutting-off said FETs in said de-activated group.

15. A gain compensator circuit that determines a reference pump current for a charge pump in a phase lock loop (PLL), comprising:

a plurality of unit current sources that are arranged into at least one group, said group generating a portion of the reference pump current when said group is activated;

a voltage generator that generates a gate voltage based on a PLL control signal; and

a switch that is connected to said group of unit current sources, wherein said switch is controlled by a corresponding capacitor control signal that also controls a fixed capacitor in a VCO tuning circuit, wherein said switch connects said gate voltage to said corresponding group of unit current sources according to said capacitor control signal.

23. A method of compensating the gain of a phase lock loop (PLL), comprising the steps of:

(1) generating a reference scale current;

(2) switching a fixed capacitor into a VCO tuning circuit that is part of a VCO to tune a frequency of said VCO;

(3) replicating said reference scale current a number of times when said fixed capacitor is switched-in to said VCO tuning circuit, wherein the number of times said reference scale current is replicated is based on said fixed capacitor; and

(4) contributing said replicated currents to a reference charge pump current for said PLL.

27. A method of compensating the gain of a phase lock loop (PLL), comprising the steps of:

(1) receiving at least one capacitor control signal that controls a corresponding fixed capacitor in a VCO tuning circuit;

(2) generating a reference scale current;

(3) activating a group of unit current sources based on said capacitor control signal;

(4) replicating said reference scale current a number of times in said activated group, wherein said number of times said reference scale current is replicated is based on said fixed capacitor that is controlled by said capacitor control signal; and

(5) summing together said replicated currents to form a reference charge pump current for said PLL.