Dynamic dram refresh rate adjustment based on cell leakage monitoring
First Claim
1. A method of adjusting a dynamic DRAM refresh rate based on cell leakage monitoring, comprising:
- directly measuring the leakage rate of a cell of a DRAM; and
adjusting a cell refresh rate based on the measured leakage rate.
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Abstract
A novel DRAM refresh method and system and a novel method of designing a low-power leakage monitoring device. With the DRAM refresh method, the refresh cycle time is adjusted based directly on the cell leakage condition. The method of designing a low-power leakage monitoring devices uses a memory cell identical to the cells in the real array. This monitor cell is designed so that it will represent the average cell or the worst cell leakage condition. If the leakage is severe, the refresh cycle time is significantly reduced, or halved. If the leakage level is very low or undetectable, then the refresh cycle time is significantly increased, or doubled. If the leakage is moderate, or in the normal range, the refresh time is optimized, so that the power consumption used for DRAM refresh is minimized. The advantages of this method over the existing method, that is, adjusting the refresh cycle time based on chip temperature include (1) the contributions from non-temperature dependent leakage factors are taken into consideration, (2) the present invention does not require different process steps, or extra process costs to integrate such device in the chip, and (3) the present invention is a straight forward method, the monitor cell does not need any calibration. In addition, its leakage mechanism and reliability concern are all identical to the cells in a real array.
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Citations
19 Claims
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1. A method of adjusting a dynamic DRAM refresh rate based on cell leakage monitoring, comprising:
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directly measuring the leakage rate of a cell of a DRAM; and
adjusting a cell refresh rate based on the measured leakage rate. - View Dependent Claims (2, 3, 4, 5)
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6. A method of designing a low-power DRAM leakage monitoring device, comprising:
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fabricating the DRAM with an array of generically uniform memory cells; and
specifically designing at least one of the memory cells to represent the average or the worst cell leakage condition. - View Dependent Claims (7, 8, 9)
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10. A dynamic random access memory, comprising:
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an array of memory cells integrally formed in the DRAM;
a cell leakage monitoring circuit integrally formed in the DRAM to directly measure the leakage rate of at least one of the cells of the DRAM; and
a refresh rate adjustment circuit to adjust a cell refresh rate based on the measured leakage rate. - View Dependent Claims (11, 12, 14, 15, 16, 17, 18, 19)
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13. A method for refreshing the cells of a DRAM, comprising:
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issuing a refresh command to pre-charge a monitor cell and to activate a self-refresh circuit;
the self-refresh circuit starting a refresh operation from a first word-line address to a last word-line address;
after refreshing the last word-line address, evaluating the monitor cell;
after evaluating the monitor cell, recharging the monitor cell;
using the result of the evaluation to adjust the refresh cycle time through a control circuit; and
using the adjusted refresh cycle time in the next refresh cycle from the first word-line to the last word-line.
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Specification