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Semiconductor memory with refresh and method for operating the semiconductor memory

  • US 20020136077A1
  • Filed: 03/25/2002
  • Published: 09/26/2002
  • Est. Priority Date: 03/23/2001
  • Status: Active Grant
First Claim
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1. A semiconductor memory, comprising:

  • at least one memory cell;

    a bit line connected to said memory cell;

    a sense amplifier having an output, said sense amplifier;

    connected to said bit line;

    amplifying a signal read from said memory cell; and

    generating, at said output, an output signal derived from the signal; and

    an adiabatic amplifier connected to said bit line and to said output and driven by the output signal of said sense amplifier to write back the signal read from said memory cell to said memory cell in amplified form dependent upon the output signal of said sense amplifier.

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