Semiconductor memory with refresh and method for operating the semiconductor memory
First Claim
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1. A semiconductor memory, comprising:
- at least one memory cell;
a bit line connected to said memory cell;
a sense amplifier having an output, said sense amplifier;
connected to said bit line;
amplifying a signal read from said memory cell; and
generating, at said output, an output signal derived from the signal; and
an adiabatic amplifier connected to said bit line and to said output and driven by the output signal of said sense amplifier to write back the signal read from said memory cell to said memory cell in amplified form dependent upon the output signal of said sense amplifier.
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Abstract
To carry out a refresh operation, a semiconductor memory having dynamic memory cells includes a sense amplifier that, on the output side, provides a signal depending on a control of a bit line driver. The bit line driver is embodied as an adiabatic amplifier, preferably, having current paths through which charges that are to be exchanged during a charge-reversal operation are buffer-stored in capacitors. Power loss for the charge reversal of the bit line capacitances is thereby saved. A method for operating the memory is also provided.
6 Citations
15 Claims
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1. A semiconductor memory, comprising:
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at least one memory cell;
a bit line connected to said memory cell;
a sense amplifier having an output, said sense amplifier;
connected to said bit line;
amplifying a signal read from said memory cell; and
generating, at said output, an output signal derived from the signal; and
an adiabatic amplifier connected to said bit line and to said output and driven by the output signal of said sense amplifier to write back the signal read from said memory cell to said memory cell in amplified form dependent upon the output signal of said sense amplifier. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 12)
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11. A two-mode semiconductor memory, comprising:
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at least one memory cell having a selection transistor and a storage capacitor;
a bit line connected to said memory cell;
a sense amplifier having an output, said sense amplifier;
connected to said bit line;
amplifying a signal read from said memory cell; and
generating, at said output, an output signal derived from the signal;
an adiabatic amplifier connected to said bit line and to said output and driven by the output signal of said sense amplifier to write back the signal read from said memory cell to said memory cell in amplified form dependent upon the output signal of said sense amplifier;
said adiabatic amplifier refreshing a charge content of said storage capacitor; and
a first operating mode carrying out a reading or writing access of a data value at said memory cell with a relatively high power loss consumption and a second operating mode refreshing the data value stored in said memory cell through said adiabatic amplifier with a relatively lower power loss consumption. - View Dependent Claims (14, 15)
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13. A method for operating a semiconductor memory, which comprises:
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providing a two-mode semiconductor memory having;
at least one memory cell;
a bit line connected to the memory cell;
a sense amplifier having an output, the sense amplifier connected to the bit line; and
an adiabatic amplifier connected to the bit line and to the output of the sense amplifier;
generating an output signal derived from the signal at the output of the sense amplifier;
in a first operating mode, amplifying a signal read from the memory cell with the sense amplifier and providing the signal at an external output terminal of the semiconductor memory; and
in a second operating mode, feeding the output signal of the sense amplifier to the adiabatic sense amplifier to control, dependent upon the output signal of the sense amplifier, the adiabatic sense amplifier such that the signal read from the memory cell is written back to the memory cell again after adiabatic amplification.
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Specification