Orthogonal code generating circuit

• US 20020136269A1
• Filed: 01/29/2002
• Published: 09/26/2002
• Est. Priority Date: 01/30/2001
• Status: Active Grant

• Current Assignee: Socionext Inc.
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Kurabe, Asako, Matsushita, Hirofumi
• Granted Patent: US 7,031,369 B2
• Time in Patent Office: Days
• US Class Current: 375/140
• CPC Class Codes: H04J 13/0048 Walsh
• CPC Class Codes: H04J 13/12 Generation of orthogonal codes

Abstract

An orthogonal code generating circuit 10 is arranged by a counter circuit unit 12, a combination circuit unit 14 of orthogonal codes, and a control circuit unit 16. Furthermore, the combination circuit unit 14 is constructed of an AND gate 14a and an exclusive-OR gate 14b. The control circuit unit 16 outputs a decode output in response to a set code designation signal CNo. When a code generation starting signal ST is inputted, a counter circuit 12 starts to output a counter output. Both the decode output and the counter output are entered to the combination circuit unit 14 which AND-gates the corresponding output bits with each other, and thereafter, exclusively OR-gates the AND-gated outputs, and then outputs the exclusively OR-gated signal as serial data of an orthogonal code. As a consequence, since the conventional ROM unit for storing thereinto the orthogonal codes can be omitted, the circuit scale of the orthogonal code generating circuit 10 can be reduced.

Claims

1. An orthogonal code generating circuit for generating an orthogonal code which is defined as a code stream of an Hadamard matrix constructed of 2^k×

2^k (symbol “

k”

being integer larger than, or equal to

     0), comprising;

a counter circuit unit for counter-outputting code stream positional signals of said Hadamard matrix from a predetermined initial phase up to a maximum value in an increment order when a code generation starting signal is entered into said counter circuit unit;

a control circuit unit for outputting a decode output based upon a code designation signal used to designate a code number of said Hadamard matrix; and

a combination circuit unit for AND-gating said counter output derived from said counter circuit unit and said decode output derived from said control circuit unit with respect to output bits corresponding thereto, and also for exclusively OR-gating said AND-gated output bits to thereby output serial data of said orthogonal code.

2. An orthogonal code generating circuit as claimed in claim 1 wherein:

said control circuit unit outputs said decode output after plural bits of said code designation signal defined from an upper-grade bit up to a down-grade bit are replaced with each other; and

said combination circuit unit outputs an orthogonal code which is defined by said decode output as a code stream of a hierarchical orthogonal code.

3. An orthogonal code generating circuit as claimed in claim 1 wherein:

said control circuit unit outputs said decode output in such a manner that since a code length designation signal for designating a code length shorter than, or equal to a maximum code length is inputted, said code designation signal is used so as to designate a code length designated based upon said code length designation signal; and

said combination circuit unit outputs said orthogonal code made based upon said code designation signal for the designated code length.

4. An orthogonal code generating circuit as claimed in claim 1 wherein:

said counter circuit unit starts said counter output from said initial phase when a code initial phase setting value is entered, said initial phase corresponding to said code initial phase setting value.

5. An orthogonal code generating circuit as claimed in claim 2 wherein:

said control circuit unit switches said orthogonal code related to either said Hadamard matrix or said hierarchical orthogonal code when a code generation switching signal is entered.

6. An orthogonal code generating circuit as claimed in any one of claims 1 to 5, wherein said orthogonal code generating circuit is used for a demodulating process apparatus.

7. An orthogonal code generating circuit as claimed in any one of claims 1 to 5, wherein said orthogonal code generating circuit is used for a synchronizing process apparatus.

8. An orthogonal code generating circuit as claimed in any one of claims 1 to 5, wherein said orthogonal code generating circuit is used for a spreading process apparatus.

9. An orthogonal code generating circuit as claimed in claim 6, wherein, said demodulating process apparatusis used for a reception apparatus of a spectrum spread signal.

10. An orthogonal code generating circuit as claimed in claim 7, wherein, said synchronizing process apparatus is used for a reception apparatus of a spectrum spread signal.

11. An orthogonal code generating circuit as claimed in claim 8, wherein, said spreading process apparatus is used for a transmission apparatus of a spectrum spread signal.

12. An orthogonal code generating circuit as claimed in any one of claims 1 to 5, wherein said orthogonal code generating circuit is used for a base station apparatus comprising at least any one of a demodulating process apparatus, a synchronizing process apparatus, and a spreading process apparatus.

13. An orthogonal code generating circuit as claimed in any one of claims 1 to 5, wherein said orthogonal code generating circuit is used for a mobile terminal apparatus comprising at least any one of a demodulating process apparatus, a synchronizing process apparatus, and a spreading process apparatus.

14. An orthogonal code generating circuit as claimed in any one of claims 1 to 5, wherein said orthogonal code generating circuit is used for a mobile communication system which is comprised of a mobile terminal apparatus and a base station, in which at least any one of a demodulating process apparatus, a synchronizing process apparatus, and a spreading process apparatus is provided.