SEMICONDUCTOR DEVICE AND SEMICONDUCTOR SUBSTRATE, AND METHOD FOR FABRICATING THE SAME

• US 20020137249A1
• Filed: 09/14/1999
• Published: 09/26/2002
• Est. Priority Date: 09/14/1998
• Status: Active Grant

• Current Assignee: Xiamen San'An Optoelectronics Co.Ltd. (Sanan Optoelectronics Company Limited)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: ISHIDA, MASAHIRO, YURI, MASAAKI, ORITA, KENJI, IMAFUJI, OSAMU, NAKAMURA, SHINJI
• Granted Patent: US 6,617,182 B2
• Time in Patent Office: Days
• US Class Current: 438/47
• CPC Class Codes: H01L 21/0237 Materials
• CPC Class Codes: H01L 21/02389 Nitrides
• CPC Class Codes: H01L 21/0242 Crystalline insulating materials
• CPC Class Codes: H01L 21/0243 Surface structure
• CPC Class Codes: H01L 21/02433 Crystal orientation
• CPC Class Codes: H01L 21/02458 Nitrides
• CPC Class Codes: H01L 21/02494 Structure
• CPC Class Codes: H01L 21/02502 consisting of two layers
• CPC Class Codes: H01L 21/0254 Nitrides
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/02658 Pretreatments cleaning in general H01L21/02041
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 33/007 comprising nitride compounds
• CPC Class Codes: H01L 33/0075 comprising nitride compounds
• CPC Class Codes: H01L 33/0093 Wafer bonding; Removal of the growth substrate

Abstract

A semiconductor device includes: a crystalline substrate including a primary surface and a crystal plane provided within the primary surface so as to have a surface orientation different from a surface orientation of the primary surface; a semiconductor layered structure grown over the crystalline substrate; and an active region provided at a portion in the semiconductor layer structure above the crystal plane.

Claims

1. A semiconductor device, comprising:

a crystalline substrate including a primary surface and a crystal plane provided within the primary surface so as to have a surface orientation different from a surface orientation of the primary surface;

a semiconductor layered structure grown over the crystalline substrate; and

an active region provided at a portion in the semiconductor layer structure above the crystal plane.

2. A semiconductor device according to claim 1, wherein the portion in the semiconductor layer structure at which the active region is provided contains fewer defects as compared to surrounding regions.

3. A semiconductor device according to claim 1, wherein the crystal plane is a tilted surface which is tilted with respect to the primary surface of the crystalline substrate, and the active region is positioned above lattice defects which extend in a direction substantially perpendicular to the crystal plane.

4. A semiconductor device according to claim 1, wherein a convex-and-concave structure is provided in the primary surface of the crystalline substrate, and the crystal plane is part of the convex-and-concave structure.

5. A semiconductor device according to claim 4, wherein a convex portion included in the convex-and-concave structure has a forward mesa structure.

6. A semiconductor device according to claim 4, wherein a convex portion included in the convex-and-concave structure has a cross section in the shape of a triangle pointing upward from the primary surface of the crystalline substrate.

7. A semiconductor device according to claim 4, wherein the convex-and-concave structure has a periodic structure.

15. A semiconductor device according to claim 1, wherein the active region is made of a III group nitride compound material, and serves as a light emitting region of a light emitting element.

17. A semiconductor device according to claim 1, wherein the active region is made of a III group nitride compound material, and serves as a gate of a field effect transistor.

19. A semiconductor device according to claim 1, wherein the active region is made of a III group nitride compound material, and serves as a base of a bipolar transistor.

21. A semiconductor device according to claim 1, wherein the active region is made of a III group nitride compound material, and serves as a junction region of a diode.

36. A semiconductor device according to claim 1, wherein the crystal plane provided within the primary surface of the substrate extends along a <

1,1,−

2,0>

direction.

8. A semiconductor device, comprising:

a crystalline substrate;

a first semiconductor layer provided on the crystalline substrate;

a second semiconductor layer provided on the first semiconductor layer; and

an active region provided in the second semiconductor layer,

wherein each of the crystalline substrate and the first semiconductor layer includes a primary surface and a crystal plane provided at least within the primary surface so as to have a surface orientation different from a surface orientation of the primary surface.

9. A semiconductor device according to claim 8, wherein the crystal plane of the first semiconductor layer is a tilted surface which is tilted with respect to the primary surface of the first semiconductor layer, and the active region is positioned above lattice defects extending in a direction substantially perpendicular to the crystal plane of the first semiconductor layer.

10. A semiconductor device according to claim 8, wherein a convex-and-concave structure is provided over the crystalline substrate, and the crystal plane of the crystalline substrate or that of the first semiconductor layer is part of the convex-and-concave structure.

11. A semiconductor device according to claim 8, wherein the crystal plane of the first semiconductor layer is positioned above the crystal plane of the crystalline substrate.

12. A semiconductor device according to claim 10, wherein a convex portion included in the convex-and-concave structure has a forward mesa structure.

13. A semiconductor device according to claim 10, wherein a convex portion included in the convex-and-concave structure has a cross section in the shape of a triangle pointing upward from the crystalline substrate.

14. A semiconductor device according to claim 10, wherein the convex-and-concave structure has a periodic structure.

16. A semiconductor device according to claim 8, wherein the active region is made of a III group nitride compound material, and serves as a light emitting region of a light emitting element.

18. A semiconductor device according to claim 8, wherein the active region is made of a III group nitride compound material, and serves as a gate of a field effect transistor.

20. A semiconductor device according to claim 8, wherein the active region is made of a III group nitride compound material, and serves as a base of a bipolar transistor.

22. A semiconductor device according to claim 8, wherein the active region is made of a III group nitride compound material, and serves as a junction region of a diode.

24. A method according to claim 23, wherein the crystal plane forming step includes the steps of forming a mask having a predetermined pattern on the substrate, and selectively etching a portion of the substrate not covered with the mask.

25. A method according to claim 23, wherein the substrate is made of Al_xGa_1-xN (0≦

x≦

1), and the semiconductor layered structure forming step includes the step of forming an Al_yGa_1-yN layer (0≦

y≦

1) at a crystal growth temperature of about 900°

C. or more.

26. A method according to claim 23, wherein the substrate is made of sapphire, silicon carbide, silicon, or gallium arsenide, and the semiconductor layered structure forming step includes the steps of:

forming over the substrate, a first Al_aGa_1-aN layer (0≦

a≦

1) at a crystal growth temperature in a range of about 400°

C. to about 900°

C.; and

forming over the first Al_aGa_1-aN layer, a second Al_bGa_1-bN layer (0≦

b≦

1) at a crystal growth temperature of about 900°

C. or more.

27. A method according to claim 23, wherein the semiconductor layered structure forming step includes the step of introducing an impurity to a predetermined portion of the semiconductor layered structure at a concentration of about 10²¹ cm⁻

3 or less.

28. A method according to claim 23, wherein in the semiconductor layered structure forming step, a mole supply ratio of a V group source material to a III group source material (a V/III ratio) is about 200 or more.

30. A method according to claim 29, wherein the second semiconductor layer forming step includes the steps of:

forming a mask having a predetermined pattern on the first semiconductor layer; and

selectively etching a portion of the first semiconductor layer not covered with the mask.

31. A method according to claim 29, wherein the substrate is made of Al_xGa_1-xN (0≦

x≦

1), and the second semiconductor layer forming step includes the step of forming an Al_yGa_1-yN layer (0≦

y≦

1) at a crystal growth temperature of about 900°

C. or more.

32. A method according to claim 29, wherein the substrate is made of sapphire, silicon carbide, silicon, or gallium arsenide, and the second semiconductor layer forming step includes the steps of:

forming over the substrate, a Al_aGa_1-aN buffer layer (0≦

a≦

1) at a crystal growth temperature in a range of about 400°

C. to about 900°

C.; and

forming over the Al_aGa_1-aN buffer layer, a second Al_bGa_1-bN layer (0≦

b≦

1) at a crystal growth temperature of about 900°

C. or more.

33. A method according to claim 29, wherein the second semiconductor layer forming step includes the step of introducing an impurity to the second semiconductor layer at a concentration of about 10²¹ cm⁻

3 or less.

34. A method according to claim 29, wherein in the second semiconductor layer forming step, a mole supply ratio of a V group source material to a III group source material (a V/III ratio) is about 200 or more.

23. A method for fabricating a semiconductor device, comprising the steps of:

forming a crystal plane on a primary surf ace of a substrate so that a surface orientation of the crystal plane is different from a surf ace orientation of the primary surface of the substrate; and

forming a semiconductor layered structure made of a III group nitride compound material over the crystal plane and the primary surface of the substrate.

29. A method for fabricating a semiconductor device, comprising the steps of:

forming a first crystal plane on a primary surface of a substrate so that a surface orientation of the first crystal plane is different from a surface orientation of the primary surface of the substrate;

forming a first semiconductor layer over the crystal plane and the primary surface of the substrate;

forming a second crystal plane on a primary surface of the first semiconductor layer so that a surface orientation of the second crystal plane is different from a surface orientation of a primary surface of the first semiconductor layer; and

forming a second semiconductor layer made of a III group nitride compound material over the second crystal plane and the primary surface of the first semiconductor layer.

35. A method for fabricating a semiconductor substrate, comprising the steps of:

forming a crystal plane on a primary surface of a substrate so that a surface orientation of the crystal plane is different from a surface orientation of the primary surface of the substrate;

forming a semiconductor layer made of a III group nitride compound material over the crystal plane and the primary surface of the substrate; and

separating the semiconductor layer from the substrate.