Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements

• US 20020138716A1
• Filed: 03/22/2001
• Published: 09/26/2002
• Est. Priority Date: 03/22/2001
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: QuickSilver Controls, Inc.
• Inventors: Scheuermann, Walter James, Master, Paul L., Hogenauer, Eugene
• Granted Patent: US 6,836,839 B2
• Time in Patent Office: Days
• US Class Current: 712/227
• CPC Class Codes: G06F 13/4027 using bus bridges G06F13/4022 takes precedence
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The present invention concerns a new category of integrated circuitry and a new methodology for adaptive or reconfigurable computing. The preferred IC embodiment includes a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative in real-time to configure and reconfigure the plurality of heterogeneous computational elements for a plurality of different functional modes, including linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, memory operations, and bit-level manipulations. The various fixed architectures are selected to comparatively minimize power consumption and increase performance of the adaptive computing integrated circuit, particularly suitable for mobile, hand-held or other battery-powered computing applications.

Claims

1. An adaptive computing integrated circuit, comprising:

a plurality of heterogeneous computational elements, the plurality of heterogeneous computational elements including a first computational element and a second computational element, the first computational element having a first fixed architecture and the second computational element having a second fixed architecture, the first fixed architecture being different than the second fixed architecture; and

an interconnection network coupled to the plurality of heterogeneous computational elements, the interconnection network operative to configure the plurality of heterogeneous computational elements for a first functional mode of a plurality of functional modes, in response to first configuration information, and the interconnection network further operative to reconfigure the plurality of heterogeneous computational elements for a second functional mode of the plurality of functional modes, in response to second configuration information, the first functional mode being different than the second functional mode.

2. The adaptive computing integrated circuit of claim 1, wherein the first fixed architecture and the second fixed architecture are selected from a plurality of specific architectures, the plurality of specific architectures including functions for memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability.

3. The adaptive computing integrated circuit of claim 1, wherein the plurality of functional modes includes linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, memory operations, and bit-level manipulations.

4. The adaptive computing integrated circuit of claim 1, wherein the first fixed architecture and the second fixed architecture are selected to comparatively minimize power consumption of the adaptive computing integrated circuit.

5. The adaptive computing integrated circuit of claim 1, wherein the interconnection network reconfigurably routes data and control information between and among the plurality of heterogeneous computational elements.

6. The adaptive computing integrated circuit of claim 1, wherein the first configuration information and the second configuration information are commingled with data to form a singular bit stream.

7. The adaptive computing integrated circuit of claim 1, further comprising:

a controller coupled to the plurality of heterogeneous computational elements and to the interconnection network, the controller operative to direct and schedule the configuration of the plurality of heterogeneous computational elements for the first functional mode and the reconfiguration of the plurality of heterogeneous computational elements for the second functional mode.

8. The adaptive computing integrated circuit of claim 7, wherein the controller is further operative to time and schedule the configuration and reconfiguration of the plurality of heterogeneous computational elements with corresponding data.

9. The adaptive computing integrated circuit of claim 7, wherein the controller is further operative to select the first configuration information and the second configuration information from a singular bit stream containing data commingled with a plurality of configuration information.

10. The adaptive computing integrated circuit of claim 1, further comprising:

a memory coupled to the plurality of heterogeneous computational elements and to the interconnection network, the memory operative to store the first configuration information and the second configuration information.

11. The adaptive computing integrated circuit of claim 1, wherein the plurality of heterogeneous computational elements may be configured and reconfigured, through the interconnection network and in response to a plurality of configuration information, to implement a plurality of logic functions of a data flow graph.

12. The adaptive computing integrated circuit of claim 1, wherein the interconnection network may be further configured to perform a plurality of logic decisions of a data flow graph.

13. The adaptive computing integrated circuit of claim 1, wherein the plurality of heterogeneous computational elements may be configured to form a plurality of adaptive and heterogeneous computational units.

14. The adaptive computing integrated circuit of claim 13, wherein each computation unit of the plurality of heterogeneous computation units further includes:

a computational unit controller coupled to the plurality of heterogeneous computational elements, the computational unit controller responsive to a plurality of configuration information to generate a plurality of control bits;

a plurality of input multiplexers, the plurality of input multiplexers responsive to the plurality of control bits to select an input line from the interconnection network for the reception of input information; and

a plurality of output demultiplexers, the plurality of output demultiplexers responsive to the plurality of control bits to select a plurality of output lines from the interconnection network for the transfer of output information.

15. The adaptive computing integrated circuit of claim 13, wherein the plurality of computation units may be configured to form a plurality of reconfigurable matrices.

16. The adaptive computing integrated circuit of claim 1, wherein the adaptive computing integrated circuit is embodied within a mobile terminal having a plurality of operating modes.

17. The adaptive computing integrated circuit of claim 16, wherein the plurality of operating modes of the mobile terminal includes mobile telecommunication, personal digital assistance, multimedia reception, mobile packet-based communication, and paging.

19. The adaptive computing method of claim 18, wherein the first fixed architecture and the second fixed architecture are selected from a plurality of specific architectures, the plurality of specific architectures including functions for memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability.

20. The adaptive computing method of claim 18, wherein the plurality of functional modes includes linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, memory operations, and bit-level manipulations.

21. The adaptive computing method of claim 18, wherein the first fixed architecture and the second fixed architecture are selected to comparatively minimize power consumption of the adaptive computing integrated circuit.

22. The adaptive computing method of claim 18, further comprising:

reconfigurably routing, through the interconnection network, data and control information between and among the plurality of heterogeneous computational elements.

23. The adaptive computing method of claim 18, wherein the first configuration information and the second configuration information are commingled with data to form a singular bit stream.

24. The adaptive computing method of claim 18, further comprising:

directing and scheduling the configuration of the plurality of heterogeneous computational elements for the first functional mode and the reconfiguration of the plurality of heterogeneous computational elements for the second functional mode.

25. The adaptive computing method of claim 18, further comprising:

timing and scheduling the configuration and reconfiguration of the plurality of heterogeneous computational elements with corresponding data.

26. The adaptive computing method of claim 18, further comprising:

selecting the first configuration information and the second configuration information from a singular bit stream containing data commingled with a plurality of configuration information.

27. The adaptive computing method of claim 18, further comprising:

storing in a memory the first configuration information and the second configuration information.

28. The adaptive computing method of claim 18, wherein the plurality of heterogeneous computational elements may be configured and reconfigured, through the interconnection network and in response to a plurality of configuration information, to implement a plurality of logic functions of a data flow graph.

29. The adaptive computing method of claim 18, wherein the interconnection network may be further configured to performa plurality of logic decisions of a data flow graph.

30. The adaptive computing method of claim 18, further comprising:

generating a plurality of control bits;

in response to the plurality of control bits, select an input line from the interconnection network for the reception of input information; and

in response to the plurality of control bits, selecting an output line from the interconnection network for the transfer of output information.

31. The adaptive computing method of claim 18, wherein the adaptive computing method is operable within a mobile terminal having a plurality of operating modes.

32. The adaptive computing method of claim 31, wherein the plurality of operating modes of the mobile terminal includes mobile telecommunication, personal digital assistance, multimedia reception, mobile packet-based communication, and paging.

18. A method for adaptive computing, the comprising:

in response to first configuration information, configuring through an interconnection network a plurality of heterogeneous computational elements for a first functional mode of a plurality of functional modes, the plurality of heterogeneous computational elements including a first computational element and a second computational element, the first computational element having a first fixed architecture and the second computational element having a second fixed architecture, the first fixed architecture being different than the second fixed architecture; and

in response to second configuration information, reconfiguring through the interconnection network the plurality of heterogeneous computational elements for a second functional mode of the plurality of functional modes, the first functional mode being different than the second functional mode.

33. An adaptive computing integrated circuit, comprising:

a plurality of reconfigurable matrices, the plurality of reconfigurable matrices including a plurality of heterogeneous computation units, each heterogeneous computation unit of the plurality of heterogeneous computation units formed from a selected configuration, of a plurality of configurations, of a plurality of fixed computational elements, the plurality of fixed computational elements including a first computational element having a first architecture and a second computational element having a second architecture, the first architecture distinct from the second architecture, the plurality of heterogeneous computation units coupled to an interconnect network and reconfigurable in response to configuration information; and

a matrix interconnection network coupled to the plurality of reconfigurable matrices, the matrix interconnection network operative to reconfigure the plurality of reconfigurable matrices in response to the configuration information for a plurality of operating modes.

34. The adaptive computing integrated circuit of claim 33, wherein each computation unit of the plurality of heterogeneous computation units is selectively reconfigurable and operative to execute a distinct algorithm of a plurality of algorithms.

35. The adaptive computing integrated circuit of claim 33, further comprising:

a controller coupled to the plurality of reconfigurable matrices, the controller operative to provide the configuration information to the reconfigurable matrices and to the matrix interconnection network.

36. The adaptive computing integrated circuit of claim 35, wherein the controller is further operative to detect and select the configuration information from a singular input bit stream of commingled data and configuration information.

37. The adaptive computing integrated circuit of claim 35, wherein the controller is embodied as a predetermined configuration of a reconfigurable matrix.

38. The adaptive computing integrated circuit of claim 35, wherein the controller is further operative to direct and schedule the configuration of the plurality of fixed computational elements for the plurality of operating modes.

39. The adaptive computing integrated circuit of claim 35, wherein the controller is further operative to time and schedule the configuration and reconfiguration of the plurality of fixed computational elements with corresponding data.

40. The adaptive computing integrated circuit of claim 35, further comprising:

a memory coupled to the controller and to the plurality of reconfigurable matrices, the memory operative to store the configuration information.

41. The adaptive computing integrated circuit of claim 40, wherein the memory is embodied as a predetermined configuration of a reconfigurable matrix.

42. The adaptive computing integrated circuit of claim 33, wherein the plurality of operating modes includes a first operating mode and a second operating mode, the first operating mode being different than the second operating mode.

43. The adaptive computing integrated circuit of claim 33, wherein the first architecture and the second architecture are selected from a plurality of specific architectures, the plurality of specific architectures including functions for memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability.

44. The adaptive computing integrated circuit of claim 33, wherein the plurality of operating modes includes linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, memory operations, and bit-level manipulations.

45. The adaptive computing integrated circuit of claim 33, wherein the first architecture and the second architecture are selected to comparatively minimize power consumption of the adaptive computing integrated circuit.

46. The adaptive computing integrated circuit of claim 33, wherein an interconnection network portion of the matrix interconnection network reconfigurably routes data and control information between and among the plurality of fixed computational elements.

47. The adaptive computing integrated circuit of claim 33, wherein the configuration information is commingled with data to form a singular bit stream.

49. The adaptive computing integrated circuit of claim 48, wherein the first fixed architecture and the second fixed architecture are selected from a plurality of fixed architectures, the plurality of fixed architectures including functions for memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability.

50. The adaptive computing integrated circuit of claim 48, wherein the plurality of functional modes includes linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, memory operations, and bit-level manipulations.

51. The adaptive computing integrated circuit of claim 48, wherein the adaptive computing integrated circuit is embodied within a mobile terminal having a plurality of operating modes.

52. The adaptive computing integrated circuit of claim 51, wherein the plurality of operating modes of the mobile terminal includes mobile telecommunication, personal digital assistance, multimedia reception, mobile packet-based communication, and paging.

48. An adaptive computing integrated circuit, comprising:

a plurality of heterogeneous computational elements, the plurality of heterogeneous computational elements including a first computational element and a second computational element, the first computational element having a first fixed architecture and the second computational element having a second fixed architecture, the first fixed architecture being different than the second fixed architecture;

an interconnection network coupled to the plurality of heterogeneous computational elements, the interconnection network operative to configure the plurality of heterogeneous computational elements for a first functional mode of a plurality of functional modes, in response to first configuration information, and the interconnection network further operative to reconfigure the plurality of heterogeneous computational elements for a second functional mode of the plurality of functional modes, in response to second configuration information, the first functional mode being different than the second functional mode;

wherein a first subset of the plurality of heterogeneous computational elements is configured for a controller operating mode, the controller operating mode including functions for directing configuration and reconfiguration of the plurality of heterogeneous computational elements, for selecting the first configuration information and the second configuration information from a singular bit stream containing data commingled with a plurality of configuration information, and for scheduling the configuration and reconfiguration of the plurality of heterogeneous computational elements with corresponding data; and

wherein a second subset of the plurality of heterogeneous computational elements is configured for a memory operating mode for storing the first configuration information and the second configuration.

53. An adaptive computing integrated circuit, comprising:

a plurality of heterogeneous computational elements, the plurality of heterogeneous computational elements including a first computational element and a second computational element, the first computational element having a first fixed architecture and the second computational element having a second fixed architecture of a plurality of fixed architectures, the first fixed architecture being different than the second fixed architecture, and the plurality of fixed architectures including functions for memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability; and

an interconnection network coupled to the plurality of heterogeneous computational elements, the interconnection network operative to configure the plurality of heterogeneous computational elements for a first functional mode of a plurality of functional modes, in response to first configuration information, and the interconnection network further operative to reconfigure the plurality of heterogeneous computational elements for a second functional mode of the plurality of functional modes, in response to second configuration information, the first functional mode being different than the second functional mode.

54. The adaptive computing integrated circuit of claim 53, wherein the plurality of functional modes includes linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, memory operations, and bit-level manipulations.

55. The adaptive computing integrated circuit of claim 53, wherein the plurality of fixed architectures are selected to comparatively minimize power consumption of the adaptive computing integrated circuit.

56. The adaptive computing integrated circuit of claim 53, wherein the interconnection network reconfigurably routes data and control information between and among the plurality of heterogeneous computational elements.

57. The adaptive computing integrated circuit of claim 53, wherein the first configuration information and the second configuration information are commingled with data to form a singular bit stream.

58. The adaptive computing integrated circuit of claim 53, further comprising:

a controller coupled to the plurality of heterogeneous computational elements and to the interconnection network, the controller operative to direct and schedule the configuration of the plurality of heterogeneous computational elements for the first functional mode and the reconfiguration of the plurality of heterogeneous computational elements for the second functional mode.

59. The adaptive computing integrated circuit of claim 58, wherein the controller is further operative to time and schedule the configuration and reconfiguration of the plurality of heterogeneous computational elements with corresponding data.

60. The adaptive computing integrated circuit of claim 59, wherein the controller is further operative to select the first configuration information and the second configuration information from a singular bit stream containing data commingled with a plurality of configuration information.

61. The adaptive computing integrated circuit of claim 53, further comprising:

a memory coupled to the plurality of heterogeneous computational elements and to the interconnection network, the memory operative to store the first configuration information and the second configuration information.

62. The adaptive computing integrated circuit of claim 53, wherein the adaptive computing integrated circuit is embodied within a mobile terminal having a plurality of operating modes.

63. The adaptive computing integrated circuit of claim 62, wherein the plurality of operating modes of the mobile terminal includes mobile telecommunication, personal digital assistance, multimedia reception, mobile packet-based communication, and paging.

64. An adaptive computing integrated circuit, comprising:

a plurality of heterogeneous computational elements, the plurality of heterogeneous computational elements including a first computational element and a second computational element, the first computational element having a first fixed architecture and the second computational element having a second fixed architecture, the first fixed architecture being different than the second fixed architecture; and

an interconnection network coupled to the plurality of heterogeneous computational elements, the interconnection network operative to configure the plurality of heterogeneous computational elements for a first functional mode of a plurality of functional modes, in response to first configuration information, and the interconnection network further operative to reconfigure the plurality of heterogeneous computational elements for a second functional mode of the plurality of functional modes, in response to second configuration information, the first functional mode being different than the second functional mode, and the plurality of functional modes including linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, memory operations, and bit-level manipulations.

65. The adaptive computing integrated circuit of claim 64, wherein the first fixed architecture and the second fixed architecture are selected from a plurality of specific architectures, the plurality of specific architectures including functions for memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability.

66. The adaptive computing integrated circuit of claim 64, wherein the first fixed architecture and the second fixed architecture are selected to comparatively minimize power consumption of the adaptive computing integrated circuit.

67. The adaptive computing integrated circuit of claim 64, wherein the interconnection network reconfigurably routes data and control information between and among the plurality of heterogeneous computational elements.

68. The adaptive computing integrated circuit of claim 64, wherein the first configuration information and the second configuration information are commingled with data to form a singular bit stream.

69. The adaptive computing integrated circuit of claim 64, further comprising:

a controller coupled to the plurality of heterogeneous computational elements and to the interconnection network, the controller operative to direct and schedule the configuration of the plurality of heterogeneous computational elements for the first functional mode and the reconfiguration of the plurality of heterogeneous computational elements for the second functional mode.

70. The adaptive computing integrated circuit of claim 69, wherein the controller is further operative to time and schedule the configuration and reconfiguration of the plurality of heterogeneous computational elements with corresponding data.

71. The adaptive computing integrated circuit of claim 69, wherein the controller is further operative to select the first configuration information and the second configuration information from a singular bit stream containing data commingled with a plurality of configuration information.

72. The adaptive computing integrated circuit of claim 64, further comprising:

a memory coupled to the plurality of heterogeneous computational elements and to the interconnection network, the memory operative to store the first configuration information and the second configuration information.

73. The adaptive computing integrated circuit of claim 64, wherein the adaptive computing integrated circuit is embodied within a mobile terminal having a plurality of operating modes.

74. The adaptive computing integrated circuit of claim 73, wherein the plurality of operating modes of the mobile terminal includes mobile telecommunication, personal digital assistance, multimedia reception, mobile packet-based communication, and paging.