Monolithic series/parallel led arrays formed on highly resistive substrates

• US 20020139987A1
• Filed: 03/29/2001
• Published: 10/03/2002
• Est. Priority Date: 03/29/2001
• Status: Active Grant

• Current Assignee: Lumileds LLC (Apollo Global Management, Inc.), Philips Lumileds Lighting Company LLC (Apollo Global Management, Inc.)
• Original Assignee: Lumileds Lighting US LLC (Apollo Global Management, Inc.)
• Inventors: Collins, William David III, Bhat, Jerome Chandra, Steigerwald, Daniel Alexander
• Granted Patent: US 6,547,249 B2
• Time in Patent Office: Days
• US Class Current: 257/88
• CPC Class Codes: H01L 2224/24137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
• CPC Class Codes: H01L 2224/92244 the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 27/153 in a repetitive configuration, e.g. LED bars
• CPC Class Codes: H01L 27/156 two-dimensional arrays
• CPC Class Codes: H01L 33/08 with a plurality of light emitting regions, e.g. laterally discontinuous light emitting layer or photoluminescent region integrated within the semiconductor body H01L27/15 takes precedence
• CPC Class Codes: H01L 33/508 having a non-uniform spatial arrangement or non-uniform concentration, e.g. patterned wavelength conversion layer, wavelength conversion layer with a concentration gradient of the wavelength conversion material

Abstract

Series or parallel LED arrays are formed on a highly resistive substrate, such that both the p- and n-contacts for the array are on the same side of the array. The individual LEDs are electrically isolated from each other by trenches or by ion implantation. Interconnects deposited on the array connects the contacts of the individual LEDs in the array. In some embodiments, the LEDs are III-nitride devices formed on sapphire substrates. In one embodiment, two LEDs formed on a single substrate are connected in antiparallel to form a monolithic electrostatic discharge protection circuit. In one embodiment, multiple LEDs formed on a single substrate are connected in series . In one embodiment, multiple LEDs formed on a single substrate are connected in parallel. In some embodiments, a layer of phosphor covers a portion of the substrate on which one or more individual LEDs is formed.

Claims

1. An array of light emitting devices formed on a highly resistive substrate, the array comprising:

a first light emitting device, comprising;

a first n-type layer overlying a first portion of the substrate;

a first active region overlying the first n-type layer;

a first p-type layer overlying the first active region;

a first n-contact connected to the first n-type layer;

a first p-contact connected to the first p-type layer, wherein the first n-contact and the first p-contact are formed on the same side of the device;

a second light emitting device, comprising;

a second n-type layer overlying a second portion of the substrate;

a second active region overlying the second n-type layer;

a second p-type layer overlying the second active region;

a second n-contact connected to the second n-type layer;

a second p-contact connected to the second p-type layer, wherein the second n-contact and the second p-contact are formed on the same side of the device;

one of a trench and an ion implanted region separating the first light emitting device and the second light emitting device; and

a first interconnect connecting one of the first n- and first p-contacts to one of the second n- and second p-contacts.

2. The array of claim 1 wherein the first and second n-type layers, the first and second active regions, and the first and second p-type layers comprise III-nitride layers.

3. The array of claim 1 wherein the substrate is selected from the group consisting of sapphire, SiC, and III-nitride materials.

4. The array of claim 1 wherein the first interconnect connects the first p-contact to the second n-contact, the array further comprising a second interconnect connecting the second p-contact to the first n-contact.

5. The array of claim 4 further comprising a layer of dielectric material underlying a portion of the first and second interconnects.

6. The array of claim 1 wherein the first light emitting device and the second light emitting device are connected in series.

7. The array of claim 1 wherein the first light emitting device and the second light emitting device are connected in parallel.

8. The array of claim 1 further comprising a layer of phosphor coating a surface of the first portion of the substrate opposite the first n-type layer.

9. The array of claim 1 further comprising an highly resistive layer under the first n-type layer and the second n-type layer, wherein the highly resistive layer forms the bottom of the trench.

10. The array of claim 1 further comprising:

a third light emitting device, comprising;

a third n-type layer overlying a third portion of the substrate;

a third active region overlying the third n-type layer;

a third p-type layer overlying the third active region;

a third n-contact connected to the third n-type layer;

a third p-contact connected to the third p-type layer, wherein the third n-contact and the third p-contact are formed on the same side of the device;

a fourth light emitting device, comprising;

a fourth n-type layer overlying a fourth portion of the substrate;

a fourth active region overlying the fourth n-type layer;

a fourth p-type layer overlying the fourth active region;

a fourth n-contact connected to the fourth n-type layer;

a fourth p-contact connected to the fourth p-type layer, wherein the fourth n-contact and the fourth p-contact are formed on the same side of the device;

a second interconnect connecting the first n-contact to the third p-contact;

a third interconnect connecting the second n-contact to the fourth p-contact; and

a fourth interconnect connecting the third n-contact to the fourth n-contact;

wherein said one of a trench and an ion implanted region separates each of the first, second, third, and fourth light emitting devices from each other; and

wherein said first interconnect connects the first p-contact to the second p-contact.

11. An array of 111-nitride light emitting devices formed on an highly resistive substrate, the array comprising:

a layer of a first conductivity type overlying the substrate;

a plurality of active regions overlying the layer of first conductivity type, such that an area underlying each active region in the plurality is surrounded by a portion of the layer of first conductivity type and portions of the layer of first conductivity type interpose areas underlying each active region in the plurality of active regions;

a plurality of layers of second conductivity type, overlying the plurality of active regions;

a first contact connected to the layer of first conductivity type; and

a plurality of second contacts connected to the plurality of layers of second conductivity type.

12. The array of claim 11 wherein the first contact surrounds an area underlying each active region in the plurality of active regions.

13. The array of claim 11 wherein the layer of first conductivity type comprises GaN doped with Si.

14. The array of claim 11 wherein the plurality of layers of second conductivity type comprise AlGaN doped with Mg.

15. The array of claim 11 wherein the plurality of second contacts comprise silver.

16. The array of claim 11 wherein the first contact comprises Al.

17. The array of claim 11 wherein the first contact comprises Ag.

18. The array of claim 11 wherein the substrate is selected from the group consisting of sapphire, SiC, and III-nitride materials.

19. The array of claim 11 further comprising a layer of phosphor coating a portion of a surface of the substrate underlying one of the plurality of active regions, the surface being opposite the layer of first conductivity type.

20. A method of forming an array of light emitting devices on an highly resistive substrate, the method comprising:

forming an n-type layer overlying the substrate;

forming an active region overlying the n-type layer;

forming a p-type layer overlying the active region;

etching away a portion of the n-type layer, the active region, and the p-type layer to form a trench separating a first device from a second device;

etching away a portion of the p-type layer and the active region on each of the first and second devices to expose a portion of the n-type layer;

forming first and second p-contacts on the p-type layers of the first and second device;

forming first and second n-contacts on the n-type layers of the first and second device; and

depositing an interconnect connecting one of the first n-contact and the first p-contact to one of the second n-contact and the second p-contact.