Three-dimensional memory array and method of fabrication
First Claim
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1. A memory array disposed above a substrate comprising:
- a first plurality of spaced-apart rail-stacks disposed at a first height in a first direction above the substrate, each rail-stack including a first conductor and a first semiconductor layer extending substantially the entire length of the first conductor;
a second plurality of spaced-apart conductors disposed above the first height and in a second direction different than the first direction, and an insulating layer disposed between the first rail-stack and the second conductors which is capable of being selectively breached by passing a current between one of the first and one of the second conductors to program the array.
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Abstract
A multi-level memory array is described employing rail-stacks. The rail-stacks include a conductor and semiconductor layers. The rail-stacks are generally separated by an insulating layer used to form antifuses. In one embodiment, one-half the diode is located in one rail-stack and the other half in the other rail-stack.
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Citations
111 Claims
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1. A memory array disposed above a substrate comprising:
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a first plurality of spaced-apart rail-stacks disposed at a first height in a first direction above the substrate, each rail-stack including a first conductor and a first semiconductor layer extending substantially the entire length of the first conductor;
a second plurality of spaced-apart conductors disposed above the first height and in a second direction different than the first direction, and an insulating layer disposed between the first rail-stack and the second conductors which is capable of being selectively breached by passing a current between one of the first and one of the second conductors to program the array. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25, 26, 27, 28, 29, 30, 32, 33, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 58, 60, 97, 98)
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12. A memory array disposed above a substrate comprising:
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a first plurality of parallel spaced-apart rail-stacks disposed above the substrate running in a first direction;
a second plurality of parallel spaced-apart rail-stacks disposed above the first rail-stacks, the second plurality of rail-stacks running in a second direction different than the first direction such that a projection of the second rail-stack on the first rail-stack define intersections with the first plurality of rail-stacks; and
a layer of low conducting material separating the first plurality of rail-stacks from the second plurality of rail-stacks, the layer of low conducting material at each intersection of the first and second rail-stacks separating a first conductivity type doped semiconductor material in one of the first rail-stacks from a second conductivity type doped semiconductor material in one of the second rail-stacks.
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24. In a multi-level memory having alternate levels of first spaced-apart conductors extending in one direction and second spaced-apart conductors in the other levels extending in a second direction, an improvement wherein each first conductor includes:
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a first layer of a first conductivity type doped semiconductor material disposed on one side of the conductor over substantially its entire length;
a second layer of the first conductivity type doped semiconductor material disposed on the opposite side of the conductor over substantially its entire length;
a third layer of the first conductivity type doped semiconductor material disposed on the second layer over substantially its entire length, the third layer being more lightly doped than the second layer; and
a dielectric disposed on the third layer. - View Dependent Claims (31)
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34. In a multi-level memory having alternate levels of first spaced-apart conductors extending in one direction and second spaced-apart conductors in the other levels extending in a second direction, an improvement wherein each first conductor includes:
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a first layer of a first conductivity type doped semiconductor material disposed on one side of the first conductor over substantially its entire length;
a second layer of the first conductivity type doped semiconductor material disposed on the first layer over substantially its entire length, the second layer being more lightly doped than the first layer; and
a first dielectric layer disposed on the second layer.
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45. A multi-level non-volatile memory array comprising:
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a plurality of first rail-stacks disposed at a first and third level running generally in a first direction above a substrate, each rail-stack comprising first conductors sandwiched between layers of silicon;
a plurality of second rail-stacks disposed at a second and fourth level above the substrate and running in a second direction, each of the second rail-stacks comprising second conductors sandwiched between layers of silicon, and a plurality of layers of dielectric each disposed respectively between successive levels of the first and second rail-stacks which are capable of being selectively breached to program the array.
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57. A multi-level non-volatile memory array comprising:
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a plurality of first rail-stacks disposed at a first and third level running generally in a first direction above a substrate, each rail-stack comprising first conductors sandwiched between layers of silicon;
a plurality of second rail-stacks disposed at a second and fourth level above the substrate and running in a second direction, each of the second rail-stacks comprising second conductors sandwiched between layers of silicon, and a plurality of dielectric regions disposed between levels of the first and second rail-stacks which are capable of being selectively breached to program the array. - View Dependent Claims (59)
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61. In a multi-level memory having alternate levels of first spaced-apart conductors extending in one direction and second spaced-apart conductors in the other levels extending in a second direction, an improvement wherein each of the first conductors includes:
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a first layer of a first conductivity type doped semiconductor material disposed on one side of the first conductor over substantially its entire length;
a second layer of the first conductivity type doped semiconductor material disposed on the opposite side of the first conductor over substantially its entire length;
a third layer of the first conductivity type doped semiconductor material disposed on the first layer over substantially its entire length, the third layer being more lightly doped than the first layer;
a fourth layer of the first conductivity type doped semiconductor material disposed on the second layer over substantially its entire length, the fourth layer being more lightly doped than the second layer;
a first dielectric layer disposed on the third layer. - View Dependent Claims (62, 63, 64, 65, 66, 67, 68, 69, 70, 71)
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72. A three dimensional memory array comprising:
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a plurality of first spaced-apart parallel semiconductor rails doped with a first conductivity type dopant the first rails being disposed in a first direction and disposed at even levels in the array;
a plurality of second spaced-apart parallel semiconductor rails doped with a second conductivity type dopant, the second rails being disposed in a second direction different from the first direction and disposed as odd levels in the array; and
an anti-fuse layer separating at least the intersections of the first and second rails at each level. - View Dependent Claims (73, 74, 75, 76, 77, 78, 79, 102, 103, 107, 108, 109, 110, 111)
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80. A multi-level non-volatile memory array comprising:
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a plurality of first rail-stacks disposed at a first and third level running generally in a first direction above a substrate, each rail-stack comprising first conductors sandwiched between layers of silicon;
a plurality of second rail-stacks being thicker than the first rail-stack, disposed at a second and fourth level above the substrate and running in a second direction, each of the second rail-stacks comprising second conductors sandwiched between layers of silicon, and a plurality of layers of dielectric each disposed respectively between successive levels of the first and second rail-stacks which are capable of being selectively breached to program the array. - View Dependent Claims (81, 82, 83, 84, 85, 86, 87)
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88. A method for fabricating a multi-level memory array comprising the steps of:
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depositing a metal layer;
forming at least one layer of silicon on the metal layer where the silicon is doped with a first conductivity type dopant;
masking and etching the silicon and metal layers to define a plurality of parallel, spaced-apart rail-stacks;
filling the space between the rail-stacks with a dielectric material;
planarizing the silicon layer and the dielectric material to form a planarized surface, and forming a layer of material for an antifuse on the planarized surface. - View Dependent Claims (89, 90, 91, 92, 93, 94, 95)
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96. A method for fabricating a multi-level memory array comprising the steps of:
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forming a metal layer;
forming a first silicon layer heavily doped with a first conductivity type dopant on the metal layer;
depositing a second silicon layer on the first silicon layer, the second silicon layer being more lightly doped than the first layer with the first conductivity type dopant;
forming a layer of an antifuse material on the second silicon layer;
depositing a third silicon layer on the layer of antifuse material heavily doped with a second conductivity type dopant;
defining spaced-apart rail-stacks from the conductive layer, first and second silicon layers, the layer of antifuse material and third silicon layer;
filling space between the rail-stacks with a dielectric, and planarizing the upper surface of the dielectric fill and the third silicon layer.
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99. A method for fabricating a multi-level memory array comprising the steps of:
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forming a conductor layer;
forming a first silicon layer doped with a first conductivity type dopant on the conductive layer;
forming a second silicon layer on the first silicon layer, the second silicon layer being more lightly doped than the first layer with the first conductivity type dopant;
forming a layer of an antifuse material on the second silicon layer;
forming a third silicon layer on the layer of antifuse material doped with a second conductivity type dopant;
defining spaced-apart first rail-stacks from the conductive layer, the first and second silicon layers, the layer of antifuse material and the third silicon layer;
filling between the first rail-stacks with a dielectric, and planarizing the upper surface of the dielectric fill and the third silicon layer. - View Dependent Claims (100, 101)
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104. A method for fabricating a multi-level memory array comprising the steps of:
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forming a first silicon layer lightly doped with a first conductivity type dopant;
forming a second silicon layer more heavily doped than the first layer with the first conductivity type dopant;
depositing a conductive layer on the second silicon layer;
depositing a third silicon layer heavily doped with a second conductivity type dopant;
etching the first, second and third silicon layers and conductive layers to define a plurality of parallel, spaced-apart rail-stacks;
filling the space between the rail-stacks with a dielectric material;
planarizing the third silicon layer and the dielectric filling material, and depositing a layer of an antifuse material on the planarized surface. - View Dependent Claims (105, 106)
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Specification