Three-dimensional memory array and method of fabrication

• US 20020140051A1
• Filed: 05/22/2002
• Published: 10/03/2002
• Est. Priority Date: 04/28/2000
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Johan N. Knall, Mark Johnson
• Inventors: Johnson, Mark, Knall, N. Johan
• Granted Patent: US 6,653,712 B2
• Time in Patent Office: Days
• US Class Current: 257/530
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: H01L 21/822 the substrate being a semiconductor, using silicon technology H01L21/8258 takes precedence
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/101 including resistors or capacitors only
• CPC Class Codes: H01L 27/1021 including diodes only

Abstract

A multi-level memory array is described employing rail-stacks. The rail-stacks include a conductor and semiconductor layers. The rail-stacks are generally separated by an insulating layer used to form antifuses. In one embodiment, one-half the diode is located in one rail-stack and the other half in the other rail-stack.

Claims

1. A memory array disposed above a substrate comprising:

a first plurality of spaced-apart rail-stacks disposed at a first height in a first direction above the substrate, each rail-stack including a first conductor and a first semiconductor layer extending substantially the entire length of the first conductor;

a second plurality of spaced-apart conductors disposed above the first height and in a second direction different than the first direction, and

an insulating layer disposed between the first rail-stack and the second conductors which is capable of being selectively breached by passing a current between one of the first and one of the second conductors to program the array.

2. The array defined by claim 1 wherein the first semiconductor layer is a silicon layer.

3. The array defined by claim 2 wherein the first and second conductors are perpendicular to one another.

4. The array defined by claim 3 wherein the first silicon layer is more heavily doped adjacent to the first conductor than it is at its surface spaced-apart from the first conductor.

5. The array defined by claim 4 wherein the second conductors have a second silicon layer disposed on the second conductors extending substantially the entire length of the second conductors.

6. The array defined by claim 4 wherein the insulating layer is on the surface of the first silicon layer spaced-apart from the first conductor.

7. The array defined by claim 6 wherein the second conductors are on the insulating layer.

8. The array defined by claim 7 wherein the silicon is doped with an n-type dopant.

9. The array defined by claim 8 wherein Schottky diodes are formed to program the array.

10. The array defined by claim 1 wherein the insulating layer is substantially continuous between the first plurality of rail-stacks and the second plurality of conductors.

11. The array defined by claim 1 wherein the insulating layer provides a physical barrier between the first plurality of rail-stacks and the second plurality of conductors.

13. The memory array defined by claim 12 wherein the semiconductor material is silicon.

14. The memory array defined by claim 12 wherein the layer of low conducting material provides a physical barrier between the first and second plurality of rail-stacks, substantially minimizing sidewall leakage.

15. The memory array defined by claim 13 wherein the passage of a current equal to or greater than a predetermined threshold from one of the first rail-stacks to one of the second rail-stacks causes a diode to form at the intersection of these rail-stacks.

16. The memory array defined by claim 15 wherein the silicon on one side of each intersection is more lightly doped than the silicon on the opposite side of each intersection.

17. The memory array defined by claim 16 wherein the side of the intersection having the more lightly doped silicon includes a more heavily doped silicon region between the more lightly doped silicon and its respective conductor.

18. The memory array defined by claims 11 or 17 wherein the low conducting material comprises silicon dioxide.

19. The memory array defined by claims 11 or 17 wherein the low conducting material layer comprises silicon nitride.

20. The memory array defined by claims 11 or 17 wherein the low conducting material layer comprises undoped silicon.

21. The memory array defined by claims 11 or 17 wherein the first and second rail-stacks include a conductor comprising a metal or a metallic compound.

22. The memory array defined by claim 21 wherein each conductor is sandwiched between silicon in a multi-level array.

23. The memory array defined by claim 12 wherein the layer of low conductivity material is grown from a semiconductor layer.

25. The memory defined by claim 24 wherein the semiconductor material is silicon.

26. The memory defined by claim 25 wherein the dielectric is grown from the semiconductor material.

27. The memory defined by claim 26 wherein the dielectric is silicon dioxide.

28. The memory defined by claim 25 wherein the dielectric is silicon nitride.

29. The memory defined by claim 25 wherein the dielectric extends substantially continuously between the levels.

30. The memory defined by claim 24 wherein the memory is programmed by forming Schottky diodes at selected intersections of the first and second conductors.

32. The memory defined by claim 24 wherein each second conductor includes:

a fourth layer of a second conductivity type doped semiconductor material disposed on one side of the second conductor over substantially its entire length;

a fifth layer of a second conductivity type doped semiconductor material disposed on the opposite side of the second conductor over substantially its entire length;

a sixth layer of the second conductivity type doped semiconductor material disposed on the fifth layer over substantially its entire length, the sixth layer being more lightly doped than the fifth layer; and

a third dielectric disposed on the sixth layer.

33. The memory defined by claim 32 wherein the second conductivity type doped material is doped silicon.

35. The memory defined by claim 34 wherein the semiconductor material is silicon.

36. The memory of claim 35 wherein the second conductors include:

a third layer of silicon doped with a second conductivity type dopant extending over substantially its entire length; and

a second dielectric layer disposed on the third layer.

37. The memory defined by claim 38 wherein additional silicon layers are disposed on the first and second dielectric.

38. The array defined by claim 34 wherein p+n−

diodes are formed at all levels of the array where programming occurs.

39. The array defined by claim 34 wherein p−

n+ diodes are formed at all levels of the array where programming occurs.

40. The memory defined by claim 38 wherein the first dielectric layer at each level is silicon dioxide.

41. The memory defined by claim 40 wherein each dielectric layer is substantially continuous at each level.

42. The memory defined by claim 40 wherein the dielectric layer is grown from silicon.

43. The memory defined by claim 41 wherein the dielectric layer is blanket deposited.

44. The memory defined by claim 38 or 39 wherein the first dielectric layer at each level is silicon nitride.

46. The array defined by claim 45 wherein the layers of silicon on the first conductors are doped with a first conductivity type dopant and wherein the layers of silicon on the second conductor are doped with a second conductivity type dopant.

47. The array defined by claim 45 wherein the layers of dielectric are blanket deposited.

48. The array defined by claim 45 wherein the layers of dielectric are grown on the silicon.

49. The array defined by claim 45 where the layers of dielectric are substantially continuous, forming a physical barrier between levels of rail-stacks.

50. The array defined by claim 45 wherein the layers of silicon on at least one side of the first conductors are more heavily doped adjacent to the first conductor than they are further from the first conductor.

51. The array defined by claim 50 wherein p+n−

diodes are formed at all levels of the array where programming occurs.

52. The array defined by claim 38 wherein p−

n+ diodes are formed at all levels of the array where programming occurs.

53. The array defined by claim 46 wherein the layers of silicon on at least one side of the second conductors are more heavily doped adjacent to the second conductors than they are further from the second conductors.

54. The array defined by claim 50, 52, or 53 wherein the layer of dielectric comprises silicon dioxide.

55. The array defined by claim 50, 52, or 53 wherein the layer of dielectric comprises silicon nitride.

56. The array defined by claim 50 or 52 wherein the first rail-stacks and second rail-stacks form right angles.

58. The array defined by claim 57 wherein the dielectric regions are grown from one of the layers of silicon.

60. The array defined by claim 57 or 58 wherein p+n−

diodes are formed between each of the first and second rail-stacks where programming occurs.

97. The method of claim 96 including repeating the steps of claim 49 to form second lines disposed above the first lines and generally perpendicular to the first lines.

98. The method defined by claim 97 including additionally etching through the third silicon layer of the first lines in alignment with the second lines.

12. A memory array disposed above a substrate comprising:

a first plurality of parallel spaced-apart rail-stacks disposed above the substrate running in a first direction;

a second plurality of parallel spaced-apart rail-stacks disposed above the first rail-stacks, the second plurality of rail-stacks running in a second direction different than the first direction such that a projection of the second rail-stack on the first rail-stack define intersections with the first plurality of rail-stacks; and

a layer of low conducting material separating the first plurality of rail-stacks from the second plurality of rail-stacks, the layer of low conducting material at each intersection of the first and second rail-stacks separating a first conductivity type doped semiconductor material in one of the first rail-stacks from a second conductivity type doped semiconductor material in one of the second rail-stacks.

24. In a multi-level memory having alternate levels of first spaced-apart conductors extending in one direction and second spaced-apart conductors in the other levels extending in a second direction, an improvement wherein each first conductor includes:

a first layer of a first conductivity type doped semiconductor material disposed on one side of the conductor over substantially its entire length;

a second layer of the first conductivity type doped semiconductor material disposed on the opposite side of the conductor over substantially its entire length;

a third layer of the first conductivity type doped semiconductor material disposed on the second layer over substantially its entire length, the third layer being more lightly doped than the second layer; and

a dielectric disposed on the third layer.

31. The memory defined by claims 24 or 25 wherein a second dielectric is disposed on the first layer.

34. In a multi-level memory having alternate levels of first spaced-apart conductors extending in one direction and second spaced-apart conductors in the other levels extending in a second direction, an improvement wherein each first conductor includes:

a first layer of a first conductivity type doped semiconductor material disposed on one side of the first conductor over substantially its entire length;

a second layer of the first conductivity type doped semiconductor material disposed on the first layer over substantially its entire length, the second layer being more lightly doped than the first layer; and

a first dielectric layer disposed on the second layer.

45. A multi-level non-volatile memory array comprising:

a plurality of first rail-stacks disposed at a first and third level running generally in a first direction above a substrate, each rail-stack comprising first conductors sandwiched between layers of silicon;

a plurality of second rail-stacks disposed at a second and fourth level above the substrate and running in a second direction, each of the second rail-stacks comprising second conductors sandwiched between layers of silicon, and

a plurality of layers of dielectric each disposed respectively between successive levels of the first and second rail-stacks which are capable of being selectively breached to program the array.

57. A multi-level non-volatile memory array comprising:

a plurality of first rail-stacks disposed at a first and third level running generally in a first direction above a substrate, each rail-stack comprising first conductors sandwiched between layers of silicon;

a plurality of second rail-stacks disposed at a second and fourth level above the substrate and running in a second direction, each of the second rail-stacks comprising second conductors sandwiched between layers of silicon, and

a plurality of dielectric regions disposed between levels of the first and second rail-stacks which are capable of being selectively breached to program the array.

59. The array defined by claims 57 or 58 wherein p−

n+ diodes are formed between each of the first and second rail-stacks where programming occurs.

61. In a multi-level memory having alternate levels of first spaced-apart conductors extending in one direction and second spaced-apart conductors in the other levels extending in a second direction, an improvement wherein each of the first conductors includes:

a first layer of a first conductivity type doped semiconductor material disposed on one side of the first conductor over substantially its entire length;

a second layer of the first conductivity type doped semiconductor material disposed on the opposite side of the first conductor over substantially its entire length;

a third layer of the first conductivity type doped semiconductor material disposed on the first layer over substantially its entire length, the third layer being more lightly doped than the first layer;

a fourth layer of the first conductivity type doped semiconductor material disposed on the second layer over substantially its entire length, the fourth layer being more lightly doped than the second layer;

a first dielectric layer disposed on the third layer.

62. The memory of claim 61 wherein the dielectric layer is formed on the third layer by blanket deposition.

63. The memory of claim 61 wherein the dielectric layer is grown on the third layer.

64. The memory of claim 61 wherein the dielectric layer is substantially continuous over and at least two spaced-apart conductors extending in the one direction at least two spaced-apart conductors extending in the second direction.

65. The memory defined by claim 61 wherein each second conductor includes:

a fifth layer of a second conductivity type doped material disposed on one side of the second conductor over substantially its entire length;

a sixth layer of the second conductivity type doped material disposed on the opposite side of the second conductor over substantially its entire length;

a second dielectric layer disposed on the sixth layer.

66. The memory defined by claims 61 or 65 where the projection of the intersection of the first and second conductors at each level defines a p+n−

diode.

67. The memory defined in claims 61 or 65 wherein at the projection of the intersection of the first and second conductors at each level defines a p+n−

diode.

68. The memory defined by claim 61 wherein the semiconductor material is silicon.

69. The memory defined by claim 63 which the semiconductor material is silicon.

70. The memory defined by claim 68 wherein the dielectric of silicon dioxide.

71. The memory defined by claim 69 wherein the dielectric is silicon nitride.

72. A three dimensional memory array comprising:

a plurality of first spaced-apart parallel semiconductor rails doped with a first conductivity type dopant the first rails being disposed in a first direction and disposed at even levels in the array;

a plurality of second spaced-apart parallel semiconductor rails doped with a second conductivity type dopant, the second rails being disposed in a second direction different from the first direction and disposed as odd levels in the array; and

an anti-fuse layer separating at least the intersections of the first and second rails at each level.

73. The array defined by claim 72 wherein the first semiconductor rails are uniformly doped silicon rails.

74. The array defined by claim 73 wherein the second semiconductor rails are uniformly doped silicon rails.

75. The array defined by claim 72 wherein the antifuse layer is substantially continuous across the array.

76. The array defined by claims 73 or 74 wherein the antifuse material is a grown silicon dioxide layer.

77. The array defined by claims 72 or 74 wherein the antifuse material is a deposited silicon dioxide layer.

78. The array defined by claim 72 or 74 wherein the antifuse material is silicon nitride.

79. The array defined by claim 72 or 74 wherein the array is fabricated on a semiconductor substrate and each of the rails is coupled to circuitry in the substrate.

102. The method of claim 99 including repeating the steps of claim 75 to form second rail-stacks disposed above the first rail-stacks perpendicular to the first rail-stacks.

103. The method defined by claim 102 including additionally etching through the third silicon layer of the first rail-stacks in alignment with the second rail-stacks.

107. The method defined in claim 102 wherein the second silicon layer is approximately 300-3000 Å

thick.

108. The method defined in claim 102 wherein the third silicon layer is approximately 300-2000 Å

thick after planarization.

109. The method defined by claim 102 wherein the antifuse layer is a silicon dioxide layer with a thickness of approximately <

200 Å

thick.

110. The method defined by claim 102 wherein the antifuse layer is a grown silicon dioxide layer grown from the third silicon layer.

111. The method defined by claim 102 wherein the antifuse layer is a silicon nitride layer.

80. A multi-level non-volatile memory array comprising:

a plurality of first rail-stacks disposed at a first and third level running generally in a first direction above a substrate, each rail-stack comprising first conductors sandwiched between layers of silicon;

a plurality of second rail-stacks being thicker than the first rail-stack, disposed at a second and fourth level above the substrate and running in a second direction, each of the second rail-stacks comprising second conductors sandwiched between layers of silicon, and

a plurality of layers of dielectric each disposed respectively between successive levels of the first and second rail-stacks which are capable of being selectively breached to program the array.

81. The array defined by claim 80 wherein the layers of silicon on the first conductors are doped with a first conductivity type dopant and wherein the layers of silicon on the second conductor are doped with a second conductivity type dopant.

82. The array defined by claim 81 wherein the layers of silicon on at least one side of the first conductors are more heavily doped adjacent to the first conductor than they are further from the first conductor.

83. The array defined by claim 80 wherein p+n−

diodes are formed at all levels of the array where programming occurs.

84. The array defined by claim 80 wherein p−

n+ diodes are formed at all levels of the array where programming occurs.

85. The array defined by claims 80, 83, or 84 wherein the layer of dielectric comprises silicon dioxide.

86. The array defined by claim 80, 83, or 84 wherein the layer of dielectric comprises silicon nitride.

87. The array defined by claim 80, 83, or 84 wherein the first rail-stacks and second rail-stacks form right angles.

88. A method for fabricating a multi-level memory array comprising the steps of:

depositing a metal layer;

forming at least one layer of silicon on the metal layer where the silicon is doped with a first conductivity type dopant;

masking and etching the silicon and metal layers to define a plurality of parallel, spaced-apart rail-stacks;

filling the space between the rail-stacks with a dielectric material;

planarizing the silicon layer and the dielectric material to form a planarized surface, and

forming a layer of material for an antifuse on the planarized surface.

89. The method defined by claim 88 wherein the layer of antifuse material comprises a dielectric.

90. The method defined by claim 88 wherein the layer of antifuse metal comprises undoped silicon.

91. The method defined by claim 88 wherein the layer of antifuse material is grown on the rail-stacks.

92. The method defined by claim 88 wherein the layer of antifuse material is a blanket deposition on the rail-stacks and filling material.

93. The method defined by claim 89 wherein the silicon layer comprises a first silicon heavily doped with an n-type dopant and a second layer more lightly doped with the n-type dopant.

94. The method defined by claim 89 wherein the silicon layer is a heavily doped layer.

95. The method defined by claim 94 wherein the antifuse layer is approximately 80-200 Å

thick and comprises silicon dioxide.

96. A method for fabricating a multi-level memory array comprising the steps of:

forming a metal layer;

forming a first silicon layer heavily doped with a first conductivity type dopant on the metal layer;

depositing a second silicon layer on the first silicon layer, the second silicon layer being more lightly doped than the first layer with the first conductivity type dopant;

forming a layer of an antifuse material on the second silicon layer;

depositing a third silicon layer on the layer of antifuse material heavily doped with a second conductivity type dopant;

defining spaced-apart rail-stacks from the conductive layer, first and second silicon layers, the layer of antifuse material and third silicon layer;

filling space between the rail-stacks with a dielectric, and

planarizing the upper surface of the dielectric fill and the third silicon layer.

99. A method for fabricating a multi-level memory array comprising the steps of:

forming a conductor layer;

forming a first silicon layer doped with a first conductivity type dopant on the conductive layer;

forming a second silicon layer on the first silicon layer, the second silicon layer being more lightly doped than the first layer with the first conductivity type dopant;

forming a layer of an antifuse material on the second silicon layer;

forming a third silicon layer on the layer of antifuse material doped with a second conductivity type dopant;

defining spaced-apart first rail-stacks from the conductive layer, the first and second silicon layers, the layer of antifuse material and the third silicon layer;

filling between the first rail-stacks with a dielectric, and

planarizing the upper surface of the dielectric fill and the third silicon layer.

100. The method defined by claim 99 wherein the layer of antifuse material is an oxide grown on the second silicon layer.

101. The method defined by claim 100 wherein the layer of antifuse material is a deposited dielectric.

104. A method for fabricating a multi-level memory array comprising the steps of:

forming a first silicon layer lightly doped with a first conductivity type dopant;

forming a second silicon layer more heavily doped than the first layer with the first conductivity type dopant;

depositing a conductive layer on the second silicon layer;

depositing a third silicon layer heavily doped with a second conductivity type dopant;

etching the first, second and third silicon layers and conductive layers to define a plurality of parallel, spaced-apart rail-stacks;

filling the space between the rail-stacks with a dielectric material;

planarizing the third silicon layer and the dielectric filling material, and

depositing a layer of an antifuse material on the planarized surface.

105. The method defined by claim 104 wherein the conductive layer is approximately 500-1,500 Å

thick.

106. The method defined in claim 104 wherein the first silicon layer is 1000-4000 Å

thick.