System and method utilizing on-chip voltage controlled frequency modulation to manage power consumption

• US 20020140467A1
• Filed: 03/16/2001
• Published: 10/03/2002
• Est. Priority Date: 03/16/2001
• Status: Active Grant

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Hewlett-Packard Company (HP Inc.)
• Inventors: Naffziger, Samuel D., Josephson, Don D.
• Granted Patent: US 6,509,788 B2
• Time in Patent Office: Days
• US Class Current: 327/113
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A system and method are disclosed which utilize an on-chip oscillator to provide the appropriate clock frequency for components of the chip to manage power consumption by the chip. More specifically, in a preferred embodiment of the present invention, an on-chip oscillator is utilized to provide the clock frequency for the chip'"'"'s core circuitry, and such oscillator can dynamically adjust such clock frequency to manage the chip'"'"'s power consumption. Thus, such on-chip oscillator generates the processor clock instead of the usual synchronous, externally controlled clock generator. A preferred embodiment of the present invention utilizes a voltage controlled frequency oscillator to control the chip'"'"'s clock frequency in order to dynamically manage power consumption by the chip. Such oscillator is preferably operable to adjust its output frequency based on the voltage supplied to such oscillator to effectively manage the chip'"'"'s power consumption.

Claims

1. A method for managing power consumption on an integrated circuit, said method comprising:

supplying voltage to said integrated circuit;

utilizing an oscillator included on said integrated circuit to generate a clock signal to be utilized by said integrated circuit;

dynamically adjusting the clock signal'"'"'s frequency in response to changes in voltage supplied to said integrated circuit to manage power consumption of said integrated circuit.

2. The method of claim 1 further comprising:

supplying a common voltage to said oscillator and to core circuitry of said integrated circuit.

3. The method of claim 1 wherein said voltage is supplied to both said oscillator and to core circuitry of said integrated circuit.

4. The method of claim 1 wherein said dynamically adjusting the clock signal'"'"'s frequency in response to changes in voltage required by said integrated circuit includes:

decreasing said clock signal'"'"'s frequency in response to a decrease in said voltage supplied to said integrated circuit.

5. The method of claim 4 wherein said decreasing further includes:

decreasing said clock signal'"'"'s frequency to a speed that results in power delivered to said integrated circuit remaining relatively constant.

6. The method of claim 1 wherein said dynamically adjusting the clock signal'"'"'s frequency in response to changes in voltage supplied to said integrated circuit includes:

increasing said clock signal'"'"'s frequency in response to an increase in said voltage supplied to said integrated circuit.

7. The method of claim 6 wherein said increasing further includes:

increasing said clock signal'"'"'s frequency to a speed that results in power delivered to said integrated circuit remaining relatively constant.

8. The method of claim 1 further comprising:

utilizing control circuitry included on said integrated circuit to control the voltage supplied to said oscillator.

9. An integrated circuit comprising:

core circuitry; and

oscillator that outputs a clock signal that is utilized by said core circuitry, wherein said clock signal is dynamically adjustable to manage power consumption of said integrated circuit.

10. The integrated circuit of claim 9 wherein said integrated circuit is selected from the group consisting of:

microprocessor, embedded controller, network router, graphics processor, and any other application specific integrated circuit (ASIC).

11. The integrated circuit of claim 9 wherein said oscillator is a ring oscillator.

12. The integrated circuit of claim 9 wherein said oscillator is a voltage controlled oscillator that outputs said clock signal having a frequency that is dependent on a voltage supplied to said oscillator.

13. The integrated circuit of claim 12 wherein common voltage is supplied to said oscillator and said core circuitry.

14. The integrated circuit of claim 9 wherein said oscillator is operable to dynamically adjust the frequency of said clock signal responsive to the amount of voltage supplied to said core circuitry.

15. The integrated circuit of claim 14 wherein said oscillator is operable to increase the clock signal'"'"'s frequency in response to an increase in said voltage supplied to said core circuitry, and wherein said oscillator is operable to decrease the clock signal'"'"'s frequency in response to a decrease in said voltage supplied to said core circuitry.

16. The integrated circuit of claim 15 wherein said oscillator is operable to dynamically adjust the clock signal'"'"'s frequency to a speed that results in power delivered to said integrated circuit remaining relatively constant.

18. The system of claim 17 wherein said oscillator is a voltage controlled oscillator that outputs said clock signal having a frequency that is dependent on a voltage supplied to said oscillator.

19. The system of claim 18 wherein common voltage is supplied to said oscillator and said core circuitry.

20. The system of claim 17 wherein said oscillator is operable to increase said clock frequency in response to an increase in said voltage being consumed by said integrated circuit, and wherein said oscillator is operable to decrease said clock frequency in response to a decrease in said voltage being consumed by said integrated circuit.

17. A system comprising:

integrated circuit that includes an oscillator and core circuitry;

power supply for supplying voltage to said integrated circuit; and

wherein said oscillator outputs a clock frequency that is utilized by said core circuitry, and wherein said oscillator is operable to dynamically adjust said clock frequency responsive to voltage being consumed by said integrated circuit to manage power consumption of said integrated circuit.