Method of inspecting semiconductor integrated circuit which can quickly measure a cubic body

• US 20020140949A1
• Filed: 03/28/2002
• Published: 10/03/2002
• Est. Priority Date: 03/30/2001
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Corporation
• Inventors: Sasaki, Yoshihiro, Nagao, Masahiko
• Granted Patent: US 6,954,274 B2
• Time in Patent Office: Days
• US Class Current: 356/606
• CPC Class Codes: G01N 2021/8905 Directional selective optics, e.g. slits, spatial filters
• CPC Class Codes: G01N 2021/95646 Soldering
• CPC Class Codes: G01N 21/95684 Patterns showing highly reflecting parts, e.g. metallic elements

Abstract

A semiconductor integrated circuit inspecting apparatus inspecting a terminal provided on a mount surface of a semiconductor integrated circuit includes a light emitter, a photographing unit and an inspector. The light emitter emits a linear light obliquely to the mount surface. The photographing unit photographs the mount surface to which the light is emitted to output a photograph signal. The inspector inspects the terminal in accordance with the photograph signal. The photographing unit has N (N is a positive integer) photographing elements. The photograph signal is outputted respectively only from M (M is a positive integer smaller than the N) photographing elements of the N photographing elements.

Claims

1. A semiconductor integrated circuit inspecting apparatus inspecting a terminal provided on a mount surface of a semiconductor integrated circuit, comprising:

a light emitter emitting a linear light obliquely to said mount surface;

a photographing unit photographing said mount surface to which said light is emitted to output a photograph signal;

an inspector inspecting said terminal in accordance with said photograph signal, and

wherein said photographing unit has N (N is a positive integer) photographing elements, and

wherein said photograph signal is outputted respectively only from M (M is a positive integer smaller than said N) photographing elements of said N photographing elements.

2. The semiconductor integrated circuit inspecting apparatus according to claim 1, wherein only said scanning lines corresponding to said M photographing elements of said N photographing elements are scanned such that said photographing unit outputs said photograph signals.

3. The semiconductor integrated circuit inspecting apparatus according to claim 1, wherein said photographing unit has N (=n lines×

l rows) (n and l are positive integers, respectively) photographing elements, and

wherein only said scanning lines corresponding to M (=m×

l rows) (m is a positive integer smaller than said n) photographing elements of said photographing elements of n lines×

l rows are scanned such that said photographing unit outputs said photographing signals.

4. The semiconductor integrated circuit inspecting apparatus according to claim 1, wherein said light emitter and said photographing unit constitutes a sensor, and

wherein when regions on said mount surface to which said light is emitted are changed, one of said sensor and said semiconductor integrated circuit is relatively shifted with respect to the other one of said sensor and said semiconductor integrated circuit such that said M photographing elements can photograph said regions to which said light is emitted.

5. The semiconductor integrated circuit inspecting apparatus according to claim 1, further comprising:

a calculator calculating a height of said mount surface, in accordance with said photograph signal.

6. The semiconductor integrated circuit inspecting apparatus according to claim 5, wherein said calculator determines a relation between the number of dots indicative of the emission of said light and a position in a height direction of said semiconductor integrated circuit, in a photograph picture photographed by said M photographing elements to calculate a height of said mount surface, in accordance with said relation.

7. The semiconductor integrated circuit inspecting apparatus according to claim 5, further comprising:

a first controller controlling a distance between said sensor and said semiconductor integrated circuit, and

wherein said first controller controls said distance in accordance with said calculated height of said mount surface.

8. The semiconductor integrated circuit inspecting apparatus according to claim 7, wherein said first controller controls said distance such that said M photographing elements can photograph said mount surface to which said light is emitted, when said height of said mount surface is changed.

9. The semiconductor integrated circuit inspecting apparatus according to claim 5, further comprising:

a second controller controlling said photographing elements such that said M photographing elements outputting said photograph signals of said N photographing elements are changed, and

wherein said second controller controls said photographing elements such that said M photographing elements are changed, in accordance with said calculated height of said mount surface.

10. The semiconductor integrated circuit inspecting apparatus according to claim 1, wherein when said positions of said mount surface to which said light is emitted are changed from a first position to a second position, said photograph signals in which said first position is photographed are outputted only from a first photographing element group of said M photographing elements of said N photographing elements, and said photograph signals in which said second position is photographed are outputted only from a second photographing element group of said M photographing elements different from said first photographing element group of said N photographing elements.

11. The semiconductor integrated circuit inspecting apparatus according to claim 1, wherein said photographing element is a CMOS photographing element or a CCD photographing element.

12. The semiconductor integrated circuit inspecting apparatus according to claim 11, wherein CMOS photographing elements or CCD photographing elements of said N are arranged in a shape of a matrix composed of p lines and q rows (each of p and q is a positive integer), and

wherein said photograph signals are outputted only from said CMOS photographing elements or CCD photographing elements in a range of (p-α

) lines and (q-β

) rows (said α

is a positive integer smaller than said p, and said β

is a positive integer smaller than said q).

13. The semiconductor integrated circuit inspecting apparatus according to claim 1, wherein an angle between an optical axis of said light emitter and an axis line of said photographing unit is about 90 degrees.

14. The semiconductor integrated circuit inspecting apparatus according to claim 1, wherein said axis line of said photographing unit substantially coincides with an optical axis of a light reflected from said mount surface to which said light is emitted.

15. The semiconductor integrated circuit inspecting apparatus according to claim 4, further comprising:

a two-dimensional measurement photographing unit photographing a flat shape of said mount surface; and

a shifting unit shifting said two-dimensional measurement photographing unit and said sensor with respect to said semiconductor integrated circuit.

16. The semiconductor integrated circuit inspecting apparatus according to claim 1, wherein said semiconductor integrated circuit is a BGA, and

wherein said terminal is a solder ball, and

wherein said inspector measures a height of said solder ball in accordance with said photograph signal.

19. The method of inspecting a semiconductor integrated circuit according to claim 17, wherein a combination of said (c), (d), (e) and (f) constitutes the light cutting method.

20. The method of inspecting a semiconductor integrated circuit according to claim 18, wherein a combination of said (i), (j) and (k) constitutes the light cutting method.

17. A method of inspecting a semiconductor integrated circuit, which inspects a terminal provided on a mount surface of a semiconductor integrated circuit, comprising:

(a) providing a photographing unit having N (N is a positive integer) photographing elements;

(b) detecting a position of said terminal on said mount surface;

(c) obliquely emitting a linear light to said mount surface;

(d) relatively shifting an emission target of said light and said mount surface at a set speed such that said light is emitted to each of a plurality of positions of said mount surface;

(e) photographing by said photographing unit a region on said mount surface to which said light is emitted to output a photograph signal from said photographing unit; and

(f) inspecting said terminal in accordance with said photograph signal, and

wherein a plurality of said photograph signals is outputted from only M (M is a positive integer smaller than said N) photographing elements of said N photographing elements, and

wherein said set speed when said light is emitted to said terminal is set to be higher as compared with a case when said light is not emitted to said terminal, based on a result of said (b).

18. A method of inspecting a semiconductor integrated circuit, which inspects a terminal provided on a mount surface of a semiconductor integrated circuit, comprising:

(g) providing N (N is a positive integer) CMOS photographing elements or CCD photographing elements arranged in a shape of a matrix composed of p lines and q rows (each of p and q is a positive integer);

(h) detecting a position of said terminal on said mount surface;

(i) obliquely emitting a linear light to said mount surface;

(j) photographing by said photographing unit a region on said mount surface to which said light is emitted to output said photograph signal from said photographing unit; and

(k) inspecting said terminal in accordance with said photograph signal, and

wherein a plurality of said photograph signals are outputted from only M (M is a positive integer smaller than said N) CMOS photographing elements or CCD photographing elements in a range of (p-α

) lines and (q-β

) rows (said α

is a positive integer smaller than said p, and said β

is a positive integer smaller than said q) of said N CMOS photographing elements or CCD photographing elements, and

wherein said range of said (p-α

) lines and (q-β

) rows is set to include a single one of said terminal in accordance with said result of said (h).

21. A method of inspecting a semiconductor integrated circuit, comprising:

fixing a two-dimension measuring camera and a three-dimension measuring camera on a XY stage, and

measuring a sample by using said two-dimension measuring camera and said three-dimension measuring camera.