Semiconductor memory device including memory cell portion and peripheral circuit portion

• US 20020141233A1
• Filed: 03/28/2002
• Published: 10/03/2002
• Est. Priority Date: 03/29/2001
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Hosotani, Keiji, Sunouchi, Kazumasa
• Granted Patent: US 6,980,463 B2
• Time in Patent Office: Days
• US Class Current: 365/158
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: G11C 11/15 using multiple magnetic layers G11C11/155 takes precedence
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H10B 61/10 comprising components having two electrodes, e.g. diodes or MIM elements
• CPC Class Codes: H10B 61/22 of the field-effect transistor [FET] type

Abstract

A semiconductor memory device includes a first magneto resistive element disposed in a memory cell portion, a first circuit disposed in the memory cell portion, the first circuit writing data into the first magneto resistive element or reading out data from the first magneto resistive element, and at least a portion of a second circuit disposed in a region below the memory cell portion.

Claims

1. A semiconductor memory device comprising:

a first magneto resistive element disposed in a memory cell portion,

a first circuit disposed in said memory cell portion, said first circuit writing data into said first magneto resistive element or reading out data from said first magneto resistive element, and

at least a portion of a second circuit disposed in a region below said memory cell portion.

2. A semiconductor memory device according to claim 1, wherein said second circuit controls said first circuit.

3. A semiconductor memory device according to claim 2, wherein said second circuit comprises at least one of address decoders, address wirings, a sense amplifier circuit, power supply wiring and ground wiring, a word line driving transistor, and a bit line driving transistor.

4. A semiconductor memory device according to claim 1, wherein said second circuit is a logic circuit and dose not directly control said first circuit.

5. A semiconductor memory device according to claim 4, wherein said second circuit is a random logic circuit.

6. A semiconductor memory device according to claim 1, wherein said second circuit comprises:

a circuit controlling said first circuit; and

a logic circuit which dose not directly control said first circuit.

7. A semiconductor memory device according to claim 1, wherein said second circuit comprises at least one of a logic circuit which dose not directly control said first circuit, an analog circuit, MPU, and a memory circuit.

8. A semiconductor memory device according to claim 1, wherein said first circuit comprises first and second wirings used at the time of writing data and reading out data.

9. A semiconductor memory device according to claim 8, wherein said first magneto resistive element is disposed at an intersection point of said first and second wirings.

10. A semiconductor memory device according to claim 8, wherein said first circuit further comprises a rectifying element.

11. A semiconductor memory device according to claim 10, wherein said first magneto resistive element and said rectifying element are disposed at an intersection point of said first and second wirings.

12. A semiconductor memory device according to claim 1, wherein

said second circuit comprises:

third and fourth wirings; and

a second magneto resistive element connected between said third and fourth wirings and used as a contact.

13. A semiconductor memory device according to claim 12, wherein said second magneto resistive element is formed on a same level as said first magneto resistive element.

14. A semiconductor memory device according to claim 1, wherein at least the portion of said second circuit is extracted from the region below said memory cell portion to a region outside said memory cell region.

15. A semiconductor memory device according to claim 1, wherein one of said first and second wirings is formed on a same level as an uppermost layer wiring forming an LSI.

16. A semiconductor memory device according to claim 15, wherein said second circuit comprises a sixth wiring disposed below one of said first and second wirings in said memory cell portion.

17. A semiconductor memory device according to claim 16, wherein said sixth wiring is address wirings.

18. A semiconductor memory device according to claim 1, wherein

said memory cell portion comprises:

a plurality of first magneto resistive elements disposed on a same level as each other, each of said plurality of first magneto resistive elements comprising one end portion and an other end portion;

a seventh wiring connected to the one end portions of said plurality of first magneto resistive elements;

an eighth wiring connected to the other end portions of said plurality of first magneto resistive elements; and

a ninth wiring disposed away from said seventh wiring or said eighth wiring.

19. A semiconductor memory device according to claim 1, wherein said first circuit is a switching element used at the time of reading out data.

20. A semiconductor memory device according to claim 19, wherein said switching element is a transistor or a rectifying element.

21. A semiconductor memory device according to claim 1, wherein at least the portion of said second circuit is disposed in a region directly under said memory cell portion.

22. A semiconductor memory device according to claim 21, wherein the region directly under said memory cell portion is extended from an end portion of said memory cell portion to an inside region across a plurality of cells.

23. A semiconductor memory device according to claim 1, wherein said second circuit comprises at least one of a MOS transistor, a bipolar transistor, an analog element, a wiring layer, and a contact layer.