Production process for the local interconnection level using a dielectric-conducting pair on grid

• US 20020142519A1
• Filed: 02/20/2002
• Published: 10/03/2002
• Est. Priority Date: 02/21/2001
• Status: Active Grant

• Current Assignee: STMicroelectronics SA (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SA (STMicroelectronics NV)
• Inventors: Coronel, Philippe, Ferreira, Paul, Leverd, Francois
• Granted Patent: US 6,689,655 B2
• Time in Patent Office: Days
• US Class Current: 438/118
• CPC Class Codes: H01L 21/76823 transforming an insulating layer into a conductive layer
• CPC Class Codes: H01L 21/76829 characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/76841 Barrier, adhesion or liner layers
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665

Abstract

The invention relates to a process for protection of the grid of a transistor in an integrated circuit for production of a local interconnection pad straddling over the grid and the silicon substrate on which it is formed. The process consists of applying a double dielectric-conducting layer on the transistor grid into which a polysilicon layer is added in order to use the selectivity principle, which is large considering the etching of polysilicon with respect to the oxide in which the local interconnection pad is formed. Furthermore, with the process according to the invention, a silicidation treatment can be applied beforehand on the active areas of the transistor and the grid.

Claims

1. A method for the protection of a grid of a transistor in an integrated circuit to make a local interconnection pad straddling over the grid and the silicon substrate on which the grid is formed, method comprising:

depositing a nitride layer and then a polysilicon layer on a silicon substrate and on a grid to form a double the dielectric-conducting layer;

depositing a first oxide layer to cover the double dielectric-conducting layer;

removing the first oxide layer under a height of the grid to expose a top part of the double layer above the grid;

using a mask for an etching so as to remove the polysilicon layer in an area located above the grid between two consecutive transistors in order to avoid short circuits;

implanting one or more low energy doping agents in the polysilicon layer to implant only the polysilicon layer exposed by the first oxide layer to form a doped polysilicon layer;

removing the first oxide layer which is remaining;

selectively etching to remove only the part of the polysilicon layer which has not been doped;

depositing a second oxide layer; and

making a photo-engraving of the second oxide layer in order to define a recess that straddles over the grid and the silicon substrate in which the interconnection pad is formed.

2. The method according to claim 1, wherein the step of depositing a nitride layer further comprises depositing a nitride layer on a grid which has previously been covered by a silicidation layer made of cobalt silicon CoSi₂ in order to reduce an input resistance of the grid.

3. The method according to claim 1, wherein the step of making a photo-engraving includes:

selectively etching the second oxide layer located in the recess without touching the doped silicon layer above the grid; and

selectively etching the nitride layer at a bottom of the recess without touching the doped polysilicon layer in order to obtain access to an active area of the silicon substrate.

4. The method according to claim 2, wherein the step of making a photo-engraving includes:

selectively etching the second oxide layer located in the recess without touching the doped silicon layer above the grid; and

selectively etching the nitride layer at the bottom of the recess without touching the doped polysilicon layer in order to obtain access to the active area of the silicon substrate.

5. The method according to claim 1, wherein the step of using a mask and implanting one or more low energy doping agents includes implanting low energy doping agents in the polysilicon layer by using a mask in order to implant only a portion of the polysilicon layer located above the grid so as to form a doped polysilicon layer.

6. The method according to claim 2, wherein the step of using a mask and implanting one or more low energy doping agents includes implanting low energy doping agents in the polysilicon layer by using a mask in order to implant only a portion of the polysilicon layer located above the grid so as to form a doped polysilicon layer.

7. The method according to claim 3, wherein the step of using a mask and implanting one or more low energy doping agents includes implanting low energy doping agents in the polysilicon layer by using a mask in order to implant only a portion of the polysilicon layer located above the grid so as to form a doped polysilicon layer.

8. The method according to claim 1, wherein the step of depositing a nitride layer includes depositing a polysilicon germanium layer, and wherein the step of using a mask includes:

selectively etching the doped polysilicon layer located above the grid with respect to the silicon substrate over a determined depth (d) to form a side cavity between the nitride layer located above the grid and the second oxide layer;

depositing a nitride layer in order to fill the side cavity; and

removing the nitride layer in order to leave a nitride plug in the side cavity preventing short circuits.

9. The method according to claim 2, wherein the step of depositing a nitride layer includes depositing a polysilicon germanium layer, and wherein the step of using a mask includes:

selectively etching the polysilicon germanium layer which has been doped located above the grid with respect to the silicon substrate over a determined depth (d) to form a side cavity between the nitride layer located above the grid and the second oxide layer;

depositing a nitride layer in order to fill the side cavity; and

removing the nitride layer in order to leave a nitride plug in the side cavity preventing short circuits.

10. The method according to claim 3, wherein the step of depositing a nitride layer includes depositing a polysilicon germanium layer, and wherein the step of using a mask includes:

selectively etching the polysilicon germanium layer which has been doped located above the grid with respect to the silicon substrate over a determined depth (d) to form a side cavity between the nitride layer located above the grid and the second oxide layer;

depositing a nitride layer in order to fill the side cavity; and

removing the nitride layer in order to leave a nitride plug in the side cavity preventing short circuits.

11. The method according to claim 8, wherein the step of selectively etching the polysilicon germanium layer which has been doped includes selectively etching the polysilicon germanium layer which has been doped over a depth (d) using a wet etching or isotropic plasma attack type process for selective removal of the polysilicon germanium layer.

12. The method according to claim 9, wherein the step of selectively etching the polysilicon germanium layer which has been doped includes selectively etching the polysilicon germanium layer which has been doped over a depth (d) using a wet etching or isotropic plasma attack type process for selective removal of the polysilicon germanium layer.

13. The method according to claim 10, wherein the step of selectively etching the polysilicon germanium layer which has been doped includes selectively etching the polysilicon germanium layer which has been doped over a depth (d) using a wet etching or isotropic plasma attack type process for selective removal of the polysilicon germanium layer.

14. The method according to claim 7, selectively etching the polysilicon germanium layer which has been doped includes selectively etching the polysilicon germanium layer which has been doped over a depth (d) which is determined by the selective etching time for the polysilicon layer.

15. The method according to claim 10, selectively etching the polysilicon germanium layer which has been doped includes selectively etching the polysilicon germanium layer which has been doped over a depth (d) which is determined by the selective etching time for the polysilicon layer.

16. The method according to claim 1, wherein the step of removing the first oxide layer includes removing the first oxide layer by chemical attack or by mechanical-chemical polishing.

17. The method according to claim 2, wherein the step of removing the first oxide layer includes removing the first oxide layer by chemical attack or by mechanical-chemical polishing.

18. The method according to claim 3, wherein the step of removing the first oxide layer includes removing the first oxide layer by chemical attack or by mechanical-chemical polishing.

19. The method according to claim 1, wherein the step of implanting one or more low energy doping agents is done using BF2 type doping agents.

20. The method according to claim 2, wherein the step of implanting one or more low energy doping agents is done using BF2 type doping agents.

21. The method according to claim 3, wherein the step of implanting one or more low energy doping agents is done using BF2 type doping agents.

22. The method according to claim 1, wherein the step of selectively etching to remove only part of the polysilicon layer which is has not been doped includes selectively etching to remove only part of the polysilicon layer which has not been doped using KOH or NH₄OH type wet solutions.

23. The method according to claim 2, wherein the step of selectively etching to remove only part of the polysilicon layer which is has not been doped includes selectively etching to remove only part of the polysilicon layer which has not been doped using KOH or NH₄OH type wet solutions.

24. The method according to claim 3, wherein the step of selectively etching to remove only part of the polysilicon layer which is has not been doped includes selectively etching to remove only part of the polysilicon layer which has not been doped using KOH or NH₄OH type wet solutions.

25. A method for the protection of a grid of a transistor in an integrated circuit to make a local interconnection pad straddling over the grid and the silicon substrate on which the grid is formed, the method comprising:

depositing a nitride layer and then a polysilicon layer on a silicon substrate and on a grid which has previously been covered by a silicidation layer made of cobalt silicon CoSi₂ in order to reduce an input resistance of the grid so as to form a double the dielectric-conducting layer;

depositing a first oxide layer to cover the double dielectric-conducting layer;

removing the first oxide layer under a height of the grid to expose the top part of the double layer above the grid;

using a mask for an etching so as to remove the polysilicon layer in an area located above the grid between two consecutive transistors in order to avoid short circuits;

implanting one or more low energy doping agents in the polysilicon layer to implant only the polysilicon layer exposed by the first oxide layer to form a polysilicon germanium layer which has been doped;

removing the first oxide layer which is remaining by chemical attack or by mechanical-chemical polishing.;

selectively etching to remove only the part of the polysilicon layer which has not been doped;

depositing a second oxide layer; and

making a photo-engraving of the second oxide layer in order to define a recess that straddles over the grid and the silicon substrate in which the interconnection pad is formed.