Production process for the local interconnection level using a dielectric-conducting pair on grid
First Claim
1. A method for the protection of a grid of a transistor in an integrated circuit to make a local interconnection pad straddling over the grid and the silicon substrate on which the grid is formed, method comprising:
- depositing a nitride layer and then a polysilicon layer on a silicon substrate and on a grid to form a double the dielectric-conducting layer;
depositing a first oxide layer to cover the double dielectric-conducting layer;
removing the first oxide layer under a height of the grid to expose a top part of the double layer above the grid;
using a mask for an etching so as to remove the polysilicon layer in an area located above the grid between two consecutive transistors in order to avoid short circuits;
implanting one or more low energy doping agents in the polysilicon layer to implant only the polysilicon layer exposed by the first oxide layer to form a doped polysilicon layer;
removing the first oxide layer which is remaining;
selectively etching to remove only the part of the polysilicon layer which has not been doped;
depositing a second oxide layer; and
making a photo-engraving of the second oxide layer in order to define a recess that straddles over the grid and the silicon substrate in which the interconnection pad is formed.
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Accused Products
Abstract
The invention relates to a process for protection of the grid of a transistor in an integrated circuit for production of a local interconnection pad straddling over the grid and the silicon substrate on which it is formed. The process consists of applying a double dielectric-conducting layer on the transistor grid into which a polysilicon layer is added in order to use the selectivity principle, which is large considering the etching of polysilicon with respect to the oxide in which the local interconnection pad is formed. Furthermore, with the process according to the invention, a silicidation treatment can be applied beforehand on the active areas of the transistor and the grid.
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Citations
25 Claims
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1. A method for the protection of a grid of a transistor in an integrated circuit to make a local interconnection pad straddling over the grid and the silicon substrate on which the grid is formed, method comprising:
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depositing a nitride layer and then a polysilicon layer on a silicon substrate and on a grid to form a double the dielectric-conducting layer;
depositing a first oxide layer to cover the double dielectric-conducting layer;
removing the first oxide layer under a height of the grid to expose a top part of the double layer above the grid;
using a mask for an etching so as to remove the polysilicon layer in an area located above the grid between two consecutive transistors in order to avoid short circuits;
implanting one or more low energy doping agents in the polysilicon layer to implant only the polysilicon layer exposed by the first oxide layer to form a doped polysilicon layer;
removing the first oxide layer which is remaining;
selectively etching to remove only the part of the polysilicon layer which has not been doped;
depositing a second oxide layer; and
making a photo-engraving of the second oxide layer in order to define a recess that straddles over the grid and the silicon substrate in which the interconnection pad is formed. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24)
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25. A method for the protection of a grid of a transistor in an integrated circuit to make a local interconnection pad straddling over the grid and the silicon substrate on which the grid is formed, the method comprising:
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depositing a nitride layer and then a polysilicon layer on a silicon substrate and on a grid which has previously been covered by a silicidation layer made of cobalt silicon CoSi2 in order to reduce an input resistance of the grid so as to form a double the dielectric-conducting layer;
depositing a first oxide layer to cover the double dielectric-conducting layer;
removing the first oxide layer under a height of the grid to expose the top part of the double layer above the grid;
using a mask for an etching so as to remove the polysilicon layer in an area located above the grid between two consecutive transistors in order to avoid short circuits;
implanting one or more low energy doping agents in the polysilicon layer to implant only the polysilicon layer exposed by the first oxide layer to form a polysilicon germanium layer which has been doped;
removing the first oxide layer which is remaining by chemical attack or by mechanical-chemical polishing.;
selectively etching to remove only the part of the polysilicon layer which has not been doped;
depositing a second oxide layer; and
making a photo-engraving of the second oxide layer in order to define a recess that straddles over the grid and the silicon substrate in which the interconnection pad is formed.
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Specification