Semiconductor device and method for manufacturing the same

• US 20020142548A1
• Filed: 03/27/2002
• Published: 10/03/2002
• Est. Priority Date: 03/28/2001
• Status: Active Grant

• Current Assignee: ROHM Co., Ltd.
• Original Assignee: ROHM Co., Ltd.
• Inventors: Takaishi, Masaru
• Granted Patent: US 6,649,973 B2
• Time in Patent Office: Days
• US Class Current: 438/270
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A channel diffusion area (2) for forming a channel region (2a) is placed on a semiconductor layer (1), a source area (3) is formed on this area and a source electrode (7) is formed on the surface of this source area by a metal film. Then, the metal of the source electrode is allowed to spike into the source area and the channel diffusion area to form an alloy layer (7a) with the semiconductor layer, and through this alloy layer, the source electrode is made in ohmic contact with both of the source area and the channel diffusion area. As a result, it is possible to obtain a semiconductor device with an insulated gate-driving element having a construction which makes it possible to minimize the on-resistance by increasing the gate width, using the chip area of the same size, and consequently to provide a greater current.

Claims

1. A semiconductor device, which has an insulated gate-driving element, comprising:

a semiconductor layer to form a drain area;

a channel diffusion area formed on the semiconductor layer;

a source area for interposing a part of said channel diffusion area in cooperation with said drain area;

a gate electrode that is placed on a channel region which is said part of said channel diffusion through a gate oxide film;

a source electrode formed so as to be electrically connected to said source area and channel diffusion area; and

a drain electrode formed so as to be electrically connected to said drain area,

wherein said source area is formed so that at least a part of said source area places on said channel diffusion area, and said source electrode is formed on a surface of said source area by a metal film, a metal of said source electrode being allowed to spike into said source area and said channel diffusion area to form an alloy layer with said source area and said channel diffusion area, thereby said source electrode being made in ohmic contacts with both of said source area and said channel diffusion area through the alloy layer.

2. The semiconductor device according to claim 1, wherein said insulated gate-driving element is an element having a trench construction in which said gate electrode is formed in a trench of said semiconductor layer through a gate oxide film, and said channel diffusion area and said source area are formed in a longitudinal direction around said trench.

3. The semiconductor device according to claim 1, wherein said insulated gate-driving element is a planar-type element in which said gate electrode is formed on the surface of said semiconductor layer through a gate oxide film.

4. The semiconductor device according to claim 1, wherein said semiconductor layer is made of a silicon or a silicon carbide and said source electrode is made of an aluminum.

5. A semiconductor device comprising:

a semiconductor layer of a first conductivity type having a trench;

a gate oxide film formed on the surface inside said trench;

a gate electrode embedded into said trench, a channel diffusion area of a second conductivity type formed on the surface of said semiconductor layer around said gate electrode;

a source area of said first conductivity type further formed on the surface of said channel diffusion area;

an insulating film that is thickly formed through oxidation of said gate electrode on the surface side of said gate electrode;

a source electrode made of a metal directly formed on the surface of said insulating film and the surface of said source area;

an alloy layer that is formed by allowing said metal of said source electrode to spike into said source area and channel diffusion area; and

a drain electrode that is formed so as to be electrically connected to said semiconductor layer.

6. The semiconductor device according to claim 5, wherein said gate electrode and said insulating film are formed in such a manner that the surface side of said gate electrode is engraved deeper than the surface of said semiconductor layer, the insulating film is formed through oxidation of said gate electrode with said surface of the insulating film being set virtually in the same level as said surface of said source area.

7. A method for manufacturing a semiconductor device comprising the steps of:

(a) forming a trench in a first conductivity type semiconductor layer serving as a drain area, and forming a gate electrode in said trench through a gate oxide film;

(b) successively diffusing a second conductivity type impurity and a first conductivity type impurity on said semiconductor layer so that a channel diffusion area and a source area are formed in a longitudinal direction;

(c) forming a source electrode made of a metal on the surface of said source area;

(d) carrying out a thermal process to allow said metal of said source electrode to spike into said source area and said channel diffusion area so that an alloy layer for allowing said source electrode to be made in ohmic contact with said source area and said channel diffusion area is formed, and

(e) forming a drain electrode that is electrically connected to said semiconductor layer.

8. The method for manufacturing a semiconductor device according to claim 7, wherein the formation of said source electrode is carried out after having formed a contact hole in an insulating film formed on the surface of said semiconductor layer in a separate position from said gate oxide film.

9. A method for manufacturing a semiconductor device comprising the steps of:

(a′

) forming a gate electrode on the surface of a first conductivity type semiconductor layer serving as a drain area through a gate oxide film;

(b′

) successively diffusing a second conductivity type impurity and a first conductivity type impurity on said semiconductor layer around said gate electrode so that a channel diffusion area and a source area are formed so as to form a channel region under said gate electrode;

(c) forming a source electrode made of a metal on the surface of said source area;

(d) carrying out a thermal process to allow said metal of said source electrode to spike into said source area and said channel diffusion area so that an alloy layer for allowing said source electrode to be made in ohmic contact with said source area and said channel diffusion area is formed, and

(e) forming a drain electrode that is electrically connected to said semiconductor layer.

10. A method for manufacturing a semiconductor device comprising the steps of:

(a) forming a trench in a first conductivity type semiconductor layer serving as a drain area, and forming a gate electrode in said trench through a gate oxide film;

(b″

) successively diffusing a second conductivity type impurity and a first conductive impurity on said semiconductor layer in any one of the steps so that a channel diffusion area and a source area are formed in a longitudinal direction around said gate electrode;

(f) forming a thick insulating film by oxidizing the surface of said gate electrode, as well as exposing the surface of said source area;

(c′

) forming a source electrode made of a metal on the surface of said insulating film formed on said gate electrode and the exposed surface of said source area;

(d) carrying out a thermal process to allow said metal of said source electrode to spike into said source area and said channel diffusion area so that an alloy layer for allowing said source electrode to be made in ohmic contact with said source area and said channel diffusion area is formed, and

(e) forming a drain electrode that is electrically connected to said semiconductor layer.

11. The method according to claim 10, wherein prior to the formation of said insulating film on the surface side of said gate electrode, the surface of said gate electrode is engraved deeper than the surface of said semiconductor layer through etching so that said insulating film is formed so as to set the surface of said insulating film formed through said step (f) virtually in the same level as the surface of said source area exposed through said step (f).

12. The method according to claim 10, wherein prior to the formation of said insulating film on the surface side of said gate electrode, an oxidation preventive film is formed on the surface of said semiconductor layer around said gate electrode so as to oxidize only the surface of said gate electrode.