Method and apparatus for high accuracy distributed time synchronization using processor tick counters

• US 20020143998A1
• Filed: 03/30/2001
• Published: 10/03/2002
• Est. Priority Date: 03/30/2001
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Rajagopal, Priya, Durham, David M.
• Granted Patent: US 7,194,556 B2
• Time in Patent Office: Days
• US Class Current: 709/248
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators

Abstract

A method and apparatus are provided that allow processing engines to be synchronized to each other with high accuracy. In one embodiment, the invention includes obtaining a processor tick counter value from a first processing engine, comparing the obtained processor tick counter value to a processor tick counter value from a second processing engine and determining a timing offset for synchronizing the first processing engine and the second processing engine using the comparison. The invention may further include obtaining a processor tick counter value by sending a request message from the second processing engine to the first processing engine, and receiving a reply from the first processing engine at the second processing engine. The processor tick counter value at the second processing engine can be determined by recording the time at which the request message is sent and by recording the time at which the reply is received. The invention can further include obtaining a processor frequency from the first processing engine, obtaining a processor frequency from the second processing engine and correcting the timing offset for any difference between the first processing engine frequency and the second processing engine frequency

Claims

1. A method comprising:

obtaining a processor tick counter value from a first processing engine;

comparing the obtained processor tick counter value to a processor tick counter value from a second processing engine; and

determining a timing offset for synchronizing the first processing engine and the second processing engine using the comparison.

2. The method of claim 1, wherein obtaining a processor tick counter value comprises sending a request message from the second processing engine to the first processing engine, and receiving a reply from the first processing engine at the second processing engine.

3. The method of claim 2, wherein the processor tick counter value at the second processing engine is determined by recording the time at which the request message is sent.

4. The method of claim 2, wherein the processor tick counter value at the second processing engine is determined by recording the time at which the reply is received

5. The method of claim 2 further comprising repeating sending a request message, recording the time, receiving a reply, recording the time and determining a timing offset until the determined timing offsets are within a predetermined variability range.

6. The method of claim 1 further comprising applying a time stamp to a message sent from the second processor, the time stamp being determined by applying the determined timing offset.

7. The method of claim 1 further comprising receiving an instruction having an execution time and interpreting the execution time by applying the determined timing offset.

8. The method of claim 1, further comprising:

obtaining a processor frequency from the first processing engine;

obtaining a processor frequency from the second processing engine; and

correcting the timing offset for any difference between the first processing engine frequency and the second processing engine frequency.

9. A machine-readable medium having stored thereon data representing sequences of instructions which, when executed by a machine, cause the machine to perform operations comprising:

obtaining a processor tick counter value from a first processing engine;

comparing the obtained processor tick counter value to a processor tick counter value from a second processing engine; and

determining a timing offset for synchronizing the first processing engine and the second processing engine using the comparison.

10. The medium of claim 9, wherein the instructions for obtaining a processor tick counter value comprise further instructions which, when executed by the machine, cause the machine to perform further operations comprising sending a request message from the second processing engine to the first processing engine, and receiving a reply from the first processing engine at the second processing engine.

11. The medium of claim 10, further comprising instructions which, when executed by the machine, cause the machine to perform further operations comprising determining the processor tick counter value at the second processing engine by recording the time at which the request message is sent.

12. The medium of claim 10, further comprising instructions which, when executed by the machine, cause the machine to perform further operations comprising determining the processor tick counter value at the second processing engine by recording the time at which the reply is received.

13. The medium of claim 9, further comprising instructions which, when executed by the machine, cause the machine to perform further operations comprising:

obtaining a processor frequency from the first processing engine;

obtaining a processor frequency from the second processing engine; and

correcting the timing offset for any difference between the first processing engine frequency and the second processing engine frequency.

15. The network of claim 14, wherein the first processor sends the processor tick counter value as a reply to a request message from the second processing engine.

16. The network of claim 15, wherein the processor tick counter value at the second processing engine is determined by recording the time at which the request message is sent.

17. The network of claim 15, wherein the processor tick counter value at the second processing engine is determined by recording the time at which the reply is received

18. The network of claim 14, wherein the first processing engine and the second processing engine run at different frequencies and wherein the processor corrects the timing offset for the difference between the first processing engine frequency and the second processing engine frequency.

19. The network of claim 14, wherein the processor of the second processing engine applies a time stamp to a message sent from the second processing engine, the time stamp being determined by applying the determined timing offset.

20. The network of claim 14, wherein the processor of the second processing engine executes an instruction at a time based on the determined timing offset.

14. A synchronized computing network comprising:

a first processing engine having a processor tick counter;

a second processing engine having a processor tick counter;

a communications link to send a value from the processor tick counter of the first processing engine to the second processing engine at one time; and

a processor of the second processing engine to compare the processor tick counter value from the first processing engine to a processor tick counter value from the second processing engine and determine a timing offset for synchronizing the first processing engine and the second processing engine using the comparison.