Flash memory low-latency cache
First Claim
Patent Images
1. A system comprising:
- a processor; and
a memory device coupled to the processor, the memory device including;
a main memory; and
a cache memory coupled to the processor and to the main memory to increase effective access speed between the processor and the memory device.
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Abstract
A small cache memory can be incorporated with a main memory, such as a flash memory, on an integrated circuit to improve average access times between a processor and the main memory. To minimize cost and complexity, the cache memory may contain only a few words of data. The cache can also allow a suspended transfer with minimal latency when the transfer is resumed. Designing the cache memory to interface with the processor over a standard memory bus permits the cache to be implemented in a system that could otherwise have no cache memory unless the processor and/or memory bus were redesigned.
230 Citations
20 Claims
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1. A system comprising:
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a processor; and
a memory device coupled to the processor, the memory device including;
a main memory; and
a cache memory coupled to the processor and to the main memory to increase effective access speed between the processor and the memory device. - View Dependent Claims (2, 3, 4, 5)
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6. An apparatus comprising:
a memory device to couple to a processor through a bus, the memory device including;
a main memory; and
a cache memory coupled to the main memory to increase effective access speed between the processor and the memory device. - View Dependent Claims (7, 8, 9)
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10. A method, comprising:
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requesting data from an address of a main memory;
determining if the address is contained in a cache memory located on a same integrated circuit with the main memory;
retrieving the data from the cache memory if the address is contained in the cache memory;
retrieving the data from the main memory if the address is not contained in the cache memory; and
providing the retrieved data to a requester. - View Dependent Claims (11, 12, 13, 14, 15, 17, 18, 19, 20)
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16. A method, comprising:
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requesting data from a plurality of sequential addresses of a main memory in a burst transfer;
determining if the addresses are contained in a cache memory located on a same integrated circuit with the main memory;
if the addresses are contained in the cache memory, retrieving the data from the cache memory;
if the addresses are not contained in the cache memory, retrieving the data from the main memory, and placing the data and at least one of the addresses into the cache memory;
initiating a transfer of the requested data to a requester;
interrupting the transfer after transferring a first portion of the requested data;
and resuming the transfer by retrieving a second portion of the requested data from the cache memory and transferring the second portion to the requester.
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Specification
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Current AssigneeIntel NDTM US LLC (Intel Corporation)
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Original AssigneeIntel Corporation
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InventorsKendall, Terry L.
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Granted Patent
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Time in Patent OfficeDays
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Field of Search
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US Class Current711/118
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CPC Class CodesG06F 12/0246 in block erasable memory, e...G06F 12/0802 Addressing of a memory leve...
