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Status register architecture for flexible read-while-write device

  • US 20020144066A1
  • Filed: 04/03/2001
  • Published: 10/03/2002
  • Est. Priority Date: 04/03/2001
  • Status: Active Grant
First Claim
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1. An integrated circuit comprising:

  • a memory array, wherein the memory array is divided into m partitions, wherein m is an integer greater than or equal to two;

    a microcontroller coupled to a status register, wherein the status register reports status information of m memory partitions.

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