Method and apparatus for sharing TLB entries

• US 20020144079A1
• Filed: 03/30/2001
• Published: 10/03/2002
• Est. Priority Date: 03/30/2001
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Willis, Thomas E., Zahir, Achmed R.
• Granted Patent: US 7,073,044 B2
• Time in Patent Office: Days
• US Class Current: 711/205
• CPC Class Codes: G06F 12/1027 using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]

Abstract

A sharing mechanism is herein disclosed for multiple logical processors using a translation lookaside buffer (TLB) to translate virtual addresses, for example into physical addresses. The mechanism supports sharing of TLB entries among logical processors, which may access address spaces in common. The mechanism further supports private TLB entries among logical processors, which for example, may each access a different physical addr

Claims

1. An operating-system transparent method for sharing virtual address translations comprising:

accessing a virtual address translation; and

transparently identifying if the virtual address translation is sharable.

2. The method of claim 1 further comprising

providing a first sharing indication if the virtual address translation is identified as sharable.

3. The method of claim 2 further comprising

providing a second sharing indication if the virtual address translation is identified as not sharable.

4. The method of claim 2 wherein the first sharing indication indicates a set of logical processes sharing the virtual address translation.

5. The method of claim 3 wherein the second sharing indication indicates a private status for the virtual address translation.

6. The method of claim 5 wherein the second sharing indication implicitly indicates a private status for the virtual address translation.

7. The method of claim 5 wherein the first sharing indication indicates a shared status for the virtual address translation.

8. The method of claim 7 wherein the second sharing indication implicitly indicates a shared status for the virtual address translation.

9. A storage medium having executable codes stored thereon for operating-system transparent sharing of virtual address translations which, when executed by a machine, causes the machine to:

access a virtual address translation; and

transparently identify if the virtual address translation is sharable.

10. The storage medium recited in claim 9 which, when executed by a machine, further causes the machine to:

provide a first sharing indication if the virtual address translation is identified as sharable.

11. The storage medium recited in claim 10 wherein the first sharing indication, indicates a set of logical processes sharing the virtual address translation.

12. The storage medium recited in claim 10 wherein the first sharing indication, indicates a shared status for the virtual address translation.

14. The processing system of claim 13 wherein the first logical processor and the second logical processor are located on the same die.

15. The processing system of claim 14 wherein the first logical processor and the second logical processor support multithreading.

16. The processing system of claim 13 wherein the virtual address translation is to provide the first and second logical processors access to a shared cache.

17. The processing system of claim 16 wherein the sharing indication comprises a set of logical processors sharing the virtual address translation.

18. The processing system of claim 16 wherein the shared cache stores data comprising executable instructions for the first and second logical processors.

19. The processing system of claim 13 wherein the storage location to store the virtual address translation is further to store the first sharing indication if the virtual address translation may be shared.

13. A processing system providing operating-system transparent sharing of virtual address translations, the processing system comprising:

a first logical processor;

a second logical processor;

a storage location to store a virtual address translation; and

a control logic to access a first virtual address translation for the first logical processor in the storage location and to transparently produce a first sharing indication if the virtual address translation may be shared with the second logical processor.

20. An apparatus to provide operating-system transparent sharing of virtual address translations, the apparatus comprising:

a control logic to access a first virtual address translation for a first processor,

the control logic further to transparently provide a first sharing indication if the first virtual address translation may be shared with a second processor.

21. The apparatus of claim 20 wherein the control logic comprises:

circuitry to provide a sharing indication to indicate that the virtual address translation translates a virtual address for the second processor.

22. The apparatus of claim 20 wherein the control logic comprises:

a combination of circuitry and machine executable processes to compute data of a second virtual address translation for the second processor.

23. The apparatus of claim 22 wherein the combination of circuitry and machine executable processes compare the computed data of the second virtual address translation to a corresponding data of the first virtual address translation to identify if the first virtual address translation may be shared with the second processor.

24. The apparatus of claim 20 further comprising:

a translation lookaside buffer to store the virtual address translation for the first processor.

25. The apparatus of claim 24 wherein the translation lookaside buffer is further to store the first sharing indication if the first virtual address translation may be shared with a second processor.

26. The apparatus of claim 24 wherein the first virtual address translation is to provide the first and second processors access to a shared cache.

27. The apparatus of claim 26 wherein the shared cache is accessed according to physical addresses.

28. The apparatus of claim 20 wherein the control logic is further to provide a second sharing indication if the first virtual address translation may not be shared with the second processor.

29. The apparatus of claim 28 wherein the first sharing indication, indicates a set of logical processes sharing the first virtual address translation.

30. The apparatus of claim 28 wherein the second sharing indication, indicates a private status for the first virtual address translation.

31. A processor comprising:

an address translation stage including a storage array having a plurality of entries to associate virtual address data with corresponding translated address data;

a first storage element to store a first translated address data for a first entry of the plurality of entries of the storage array; and

a control logic to identify a sharability status for the first translated address data and to provide a first sharing indication to indicate if the first entry may be shared.

32. The processor of claim 31 wherein the first storage element is further to store the first sharing indication provided by the control logic.

33. The processor of claim 31 wherein the control logic comprises:

circuitry to provide a sharing indication to indicate that the virtual address translation translates a virtual address for a second processor.

34. The processor of claim 33 wherein the control logic comprises:

a combination of circuitry and state machine executable processes to compute data of a second virtual address translation for the second processor.

35. An operating -system transparent method for providing virtual address translations comprising:

installing an entry in a translation lookaside buffer; and

transparently enabling sharing of the entry by a plurality of processors. cm 36. A multithreading processor comprising;

an address translation stage including a translation lookaside buffer having a plurality of entries to translate virtual addresses to physical addresses;

a first entry of the plurality of entries to translate a first virtual address for a first process;

a control logic comprising circuitry to identify a sharability of the first entry process;

the control logic further to provide a first sharing indication to indicate if the first entry may be shared by a second process; and

a sharing indication field in the first entry to store the first sharing indication provided by the control logic.