Apparatus, method and system for fast register renaming using virtual renaming

• US 20020144090A1
• Filed: 03/30/2001
• Published: 10/03/2002
• Est. Priority Date: 03/30/2001
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Yoaz, Adi, Ronen, Ronny, Pribush, Gregory
• Granted Patent: US 6,950,928 B2
• Time in Patent Office: Days
• US Class Current: 712/217
• CPC Class Codes: G06F 9/3838 Dependency mechanisms, e.g. register scoreboarding
• CPC Class Codes: G06F 9/384 Register renaming
• CPC Class Codes: G06F 9/3854 Instruction completion, e.g. retiring, committing or graduating
• CPC Class Codes: G06F 9/3856 Reordering of instructions, e.g. using queues or age tags
• CPC Class Codes: G06F 9/3858 Result writeback, i.e. updating the architectural state or memory
• CPC Class Codes: G06F 9/3861 Recovery, e.g. branch miss-prediction, exception handling error detection or correction G06F11/00

Abstract

A method for renaming a source for use with a processor, the method including providing an instruction, building instruction dependency information based on the instruction, caching the instruction based on the instruction dependency information to provide a cached instruction, renaming a register based on the cached instruction to provide a renamed register, and multiplexing the instruction dependency information and the renamed register to rename the source.

Claims

1. A method for renaming a source for use with a processor, the method comprising:

providing at least one instruction;

building instruction dependency information based on the at least one instruction;

caching the at least one instruction with the instruction dependency information to provide cached instruction information;

renaming a register based on the cached instruction information to provide a renamed register; and

multiplexing the instruction dependency information and the renamed register to rename the source.

2. The method of claim 1, wherein the cached instruction information includes first source information, second source information and destination information.

3. The method of claim 2, wherein the first source information includes three bits, the second source information includes three bits, and the destination information includes one bit.

4. The method of claim 1, wherein the first source information and the second source information denote a rename window instruction from which the at least one instruction depends.

5. The method of claim 1, wherein a virtual ID is formed by at least one of adding, combining, concatenating or logically OR-ing upper bits from a renamer with lower bits from an instruction cache.

6. The method of claim 1, wherein:

the first source information includes three bits, the second source information includes three bits, and the destination information includes one bit;

the first source information and the second source information denote a rename window instruction from which the at least one instruction depends; and

a virtual ID is formed by at least one of adding, combining, concatenating or logically OR-ing upper bits from a renamer with lower bits from an instruction cache.

7. The method of claim 6, wherein the processor is a microprocessor.

8. A system for renaming a source for use with a processor, the system comprising:

a fetch and decoding arrangement for fetching and decoding at least one instruction from the processor;

a build-instruction-dependency arrangement for building instruction dependency information based on the at least one instruction;

an instruction cache arrangement for caching the at least one instruction with the instruction dependency information to provide cached instruction information, the build-instruction-dependency arrangement providing the instruction dependency information to the instruction cache arrangement;

a renamer arrangement for renaming a register based on the cached instruction information and for providing a renamed register; and

a multiplexing arrangement for multiplexing the instruction dependency information and the renamed register and for providing a renamed source.

9. The system of claim 8, wherein the cached instruction information includes first source information, second source information and destination information.

10. The system of claim 9, wherein the first source information includes three bits, the second source information includes three bits, and the destination information includes one bit.

11. The system of claim 8, wherein the first source information and the second source information denote a rename window instruction from which the at least one instruction depends.

12. The system of claim 8, wherein a virtual ID is formed by at least one of adding, combining, concatenating or logically OR-ing upper bits from a renamer with lower bits from an instruction cache.

13. The system of claim 8, wherein:

the first source information includes three bits, the second source information includes three bits, and the destination information includes one bit;

the first source information and the second source information denote a rename window instruction from which the at least one instruction depends; and

a virtual ID is formed by at least one of adding, combining, concatenating or logically OR-ing upper bits from a renamer with lower bits from an instruction cache.

14. The system of claim 13, wherein the processor is a microprocessor.

16. The system of claim 15, wherein the cached instruction information includes first source information, second source information and destination information.

17. The system of claim 16, wherein the first source information includes three bits, the second source information includes three bits, and the destination information includes one bit.

18. The system of claim 15, wherein the first source information and the second source information denote a rename window instruction from which the at least one instruction depends.

19. The system of claim 15, wherein a virtual ID is formed by at least one of adding, combining, concatenating or logically OR-ing upper bits from a renamer with lower bits from an instruction cache.

20. The system of claim 15, wherein:

the first source information includes three bits, the second source information includes three bits, and the destination information includes one bit;

the first source information and the second source information denote a rename window instruction from which the at least one instruction depends; and

a virtual ID is formed by at least one of adding, combining, concatenating or logically OR-ing upper bits from a renamer with lower bits from an instruction cache.

21. The system of claim 15, wherein the processor is a microprocessor.

15. A system for renaming a source for use with a processor, the system comprising:

means for fetching and decoding at least one instruction from the processor;

means for building instruction dependency information based on the at least one instruction;

means for caching the at least one instruction with the instruction dependency information and for providing cached instruction information, the means for building instruction dependency information providing the instruction dependency information to the means for caching the instruction;

means for renaming a register based on the cached instruction information and for providing a renamed register; and

means for multiplexing the instruction dependency information and the renamed register and for providing a renamed source.

22. A set of instructions residing in a storage medium, said set of instructions capable of being executed by a processor to implement a method for renaming a source for use with a processor, the method comprising:

providing at least one instruction;

building instruction dependency information based on the at least one instruction;

caching the at least one instruction with the instruction dependency information to provide cached instruction information;

renaming a register based on the cached instruction information to provide a renamed register; and

multiplexing the instruction dependency information and the renamed register to rename the source.

23. The set of instructions residing in a storage medium of claim 22, wherein the cached instruction information includes first source information, second source information and destination information.

24. The set of instructions residing in a storage medium of claim 23, wherein the first source information includes three bits, the second source information includes three bits, and the destination information includes one bit.

25. The set of instructions residing in a storage medium of claim 22, wherein the first source information and the second source information denote a rename window instruction from which the at least one instruction depends.

26. The set of instructions residing in a storage medium of claim 22, wherein a virtual ID is formed by at least one of adding, combining, concatenating or logically OR-ing upper bits from a renamer with lower bits from an instruction cache.

27. The set of instructions residing in a storage medium of claim 22, wherein:

the first source information includes three bits, the second source information includes three bits, and the destination information includes one bit;

the first source information and the second source information denote a rename window instruction from which the at least one instruction depends; and

a virtual ID is formed by at least one of adding, combining, concatenating or logically OR-ing upper bits from a renamer with lower bits from an instruction cache.

28. The set of instructions residing in a storage medium of claim 27, wherein the processor is a microprocessor.