Apparatus, method and system for fast register renaming using virtual renaming
First Claim
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1. A method for renaming a source for use with a processor, the method comprising:
- providing at least one instruction;
building instruction dependency information based on the at least one instruction;
caching the at least one instruction with the instruction dependency information to provide cached instruction information;
renaming a register based on the cached instruction information to provide a renamed register; and
multiplexing the instruction dependency information and the renamed register to rename the source.
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Abstract
A method for renaming a source for use with a processor, the method including providing an instruction, building instruction dependency information based on the instruction, caching the instruction based on the instruction dependency information to provide a cached instruction, renaming a register based on the cached instruction to provide a renamed register, and multiplexing the instruction dependency information and the renamed register to rename the source.
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Citations
28 Claims
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1. A method for renaming a source for use with a processor, the method comprising:
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providing at least one instruction;
building instruction dependency information based on the at least one instruction;
caching the at least one instruction with the instruction dependency information to provide cached instruction information;
renaming a register based on the cached instruction information to provide a renamed register; and
multiplexing the instruction dependency information and the renamed register to rename the source. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A system for renaming a source for use with a processor, the system comprising:
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a fetch and decoding arrangement for fetching and decoding at least one instruction from the processor;
a build-instruction-dependency arrangement for building instruction dependency information based on the at least one instruction;
an instruction cache arrangement for caching the at least one instruction with the instruction dependency information to provide cached instruction information, the build-instruction-dependency arrangement providing the instruction dependency information to the instruction cache arrangement;
a renamer arrangement for renaming a register based on the cached instruction information and for providing a renamed register; and
a multiplexing arrangement for multiplexing the instruction dependency information and the renamed register and for providing a renamed source. - View Dependent Claims (9, 10, 11, 12, 13, 14, 16, 17, 18, 19, 20, 21)
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15. A system for renaming a source for use with a processor, the system comprising:
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means for fetching and decoding at least one instruction from the processor;
means for building instruction dependency information based on the at least one instruction;
means for caching the at least one instruction with the instruction dependency information and for providing cached instruction information, the means for building instruction dependency information providing the instruction dependency information to the means for caching the instruction;
means for renaming a register based on the cached instruction information and for providing a renamed register; and
means for multiplexing the instruction dependency information and the renamed register and for providing a renamed source.
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22. A set of instructions residing in a storage medium, said set of instructions capable of being executed by a processor to implement a method for renaming a source for use with a processor, the method comprising:
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providing at least one instruction;
building instruction dependency information based on the at least one instruction;
caching the at least one instruction with the instruction dependency information to provide cached instruction information;
renaming a register based on the cached instruction information to provide a renamed register; and
multiplexing the instruction dependency information and the renamed register to rename the source. - View Dependent Claims (23, 24, 25, 26, 27, 28)
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Specification