Hardware architecture for fast servicing of processor interrupts

• US 20020144099A1
• Filed: 01/25/2001
• Published: 10/03/2002
• Est. Priority Date: 01/25/2001
• Status: Abandoned Application

• Current Assignee: Microchip Technology Incorporated
• Original Assignee: Microchip Technology Incorporated
• Inventors: Phoenix, Timothy J., Muro, Manuel R. Jr.
• Application Number:
  US09/769,677
• Publication Number:
  US 20020144099A1
• Time in Patent Office: Days
• US Class Current: 712/228
• CPC Class Codes: G06F 9/30101 Special purpose registers
• CPC Class Codes: G06F 9/30134 Register stacks; shift registers
• CPC Class Codes: G06F 9/30163 with implied specifier, e.g. top of stack
• CPC Class Codes: G06F 9/32 Address formation of the next instruction, e.g. by incrementing the instruction counter G06F9/38 takes precedence
• CPC Class Codes: G06F 9/3806 using address prediction, e.g. return stack, branch history buffer
• CPC Class Codes: G06F 9/462 with multiple register sets
• CPC Class Codes: G06F 9/4812 by interrupt, e.g. masked

Abstract

An improved computer processor architecture in the form of an apparatus with a mirrored stack and method of using the same are provided that enable a processor to recover from an interrupt service routine in one or zero processor instruction cycles. The architecture also removes from software the burden of preserving and maintaining the processor registers upon an interrupt event, thereby improving coding efficiency and the utilization of processor time. The architecture makes it possible to extend faster servicing of interrupts for different levels of interrupt priorities and not just a specific interrupt path. Finally, the architecture provides a mechanism for speeding up CALL and RETURN instruction execution times. In an alternate embodiment, the mirrored stack apparatus is provided with interrupt control logic that has a port to the Program Counter control logic in order to drive directly an interrupt vector address.

Claims

1. A microprocessor architecture comprising:

a central processing unit, said central processing unit is constructed and arranged to execute instructions, said central processing unit further capable of responding to an interrupt request;

a register read bus;

a multiplexer;

a register write bus connected to said multiplexer;

at least one register, said register connected to said register read bus and to said multiplexer, said register constructed and arranged to deposit data onto said register read bus and to accept data from said multiplexer;

a mirror stack memory, said mirror stack memory connected to said multiplexer, said mirror stack memory constructed and arranged to receive data from said multiplexer and to deposit data onto said multiplexer, said mirror memory stack is associated with said register; and

a mirror stack pointer, said mirror stack pointer is connected to said mirror stack memory, said stack pointer being adjusted during read operations;

wherein, during reads from said memory stack, one or more values are read from a previously pointed to location in said memory stack.

2. A microprocessor architecture as in claim 1, wherein said architecture further comprising an interrupt control logic, said interrupt control logic having a port to a program counter control logic in order to directly drive an interrupt vector address into a program counter before the completion of the execution of a current instruction.

3. A microprocessor architecture as in claim 1, wherein said register write bus is isolated from a common bus in order to enable simultaneous updates in a single system that employs multiple mirror stack memories.

4. A method of handling an interrupt of a central processing unit, said method comprising the steps of:

(a) providing a central processing unit responsive to interrupts;

(b) placing the contents of an program counter register onto an address bus, said contents of said program counter register being an address to a first instruction, said program counter register having a program counter M-stack associated with said program counter register;

(c) fetching said first instruction from a memory;

(d) capturing said first instruction in an instruction register;

(e) decoding said first instruction, if said decoded first instruction requires a read that is needed as part of said first instruction'"'"'s operation, then performing a read;

(f) during said step (e), adjusting said program counter register in order to point to a next instruction;

(g) capturing an address for said next instruction from said program counter register;

(h) if a first result from the execution of said first instruction is to be stored in said memory, then storing said first result in said memory, otherwise, if said first result from the execution of said first instruction is to be stored in a critical register, then storing said first result in said critical register and writing said first result to an M-stack associated with said critical register;

(i) determining if an interrupt, if received, will be serviced and executing a current instruction, said current instruction being an instruction predefined to be executed after said execution of said first instruction;

(j) if said interrupt is to be serviced, then enabling said program counter register to be driven with a value from an interrupt vector table that contains an address of a first interrupt service routine instruction;

(k) capturing said address of said first interrupt service routine instruction with said program counter M-stack and writing a current result from the execution of said current instruction, if said current result are to be written to a critical register, then said current result shall also be written to a mirror stack corresponding to said critical register except on the condition that if said current instruction is a branching instruction, then said current result shall be written to said program counter M-stack;

(l) executing said first interrupt service routine instruction and adjusting at least one M-stack pointer in order to store the at least one pre-interrupt register values of said critical registers;

(m) returning from said interrupt service routine; and

(n) adjusting said at least one M-stack pointer to point to said at least one pre-interrupt register values, said at least one pre-interrupt register values being simultaneously driven at a corresponding register input;

wherein after said step (n) said interrupt service routine will have ended and a starting point of the next instruction to be executed before said interrupt may be executed.

5. A method of handling an interrupt of a central processing unit as in claim 4, wherein said adjusting step (n) occurs during an execute phase.