Method and apparatus for improving reliability in microprocessors
First Claim
Patent Images
1. An apparatus for detecting errors in a multiple processor system, comprising:
- at least two processors, each processor including a plurality of pipeline stages for processing the same instructions;
wherein each pipeline stage includes a parity bit generator, the parity bit generator generating at least one parity bit for each stage; and
a comparing circuit intercoupled to the processors, the comparing circuit comparing the parity bit of a stage of one processor to the parity bit of the same stage of another processor, and indicating an error when the parity bits are different in value.
1 Assignment
0 Petitions
Accused Products
Abstract
A method and system provides an increased robustness and protection against the occurrence of soft errors in parallel connect functional redundancy checking processors. This is achieved by predicting in advance the likely occurrence of a soft error and its impact on the resulting instruction flow and using already existing circuit implementations to hide the transient error.
-
Citations
15 Claims
-
1. An apparatus for detecting errors in a multiple processor system, comprising:
-
at least two processors, each processor including a plurality of pipeline stages for processing the same instructions;
wherein each pipeline stage includes a parity bit generator, the parity bit generator generating at least one parity bit for each stage; and
a comparing circuit intercoupled to the processors, the comparing circuit comparing the parity bit of a stage of one processor to the parity bit of the same stage of another processor, and indicating an error when the parity bits are different in value. - View Dependent Claims (2, 3, 4, 5)
-
-
6. A machine-readable medium having stored thereon a plurality of executable instructions, the plurality of instructions comprising instructions to:
-
process the same instructions for at least two processors;
compare at least one parity bit of a pipeline stage for one processor with at least one parity bit of the same stage of another processor; and
indicate an error when the parity bits are different in value. - View Dependent Claims (7, 8, 9, 10)
-
-
11. A method for detecting errors in a multiple processor system, comprising:
-
processing the same instructions during a plurality of pipeline stages for at least two processors;
generating at least one parity bit for each stage;
comparing the parity bit of a stage for one processor with the parity bit of the same stage of another processor; and
indicating an error when the parity bits are different in value. - View Dependent Claims (12, 13, 14, 15)
-
Specification