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Microprocessor design support for computer system and platform validation

  • US 20020144183A1
  • Filed: 03/28/2001
  • Published: 10/03/2002
  • Est. Priority Date: 03/28/2001
  • Status: Active Grant
First Claim
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1. An integrated circuit, comprising:

  • a processing core, a data request pipeline having an arbiter in communication with the processing core, the data request pipeline having an external bus interface, and a validation FUB having an input coupled to the external bus interface of the data request pipeline.

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