Method for calculating the capacity of a layout of an integrated circuit with the aid of a computer, and application of the method to integrated circuit fabrication

• US 20020144224A1
• Filed: 04/02/2002
• Published: 10/03/2002
• Est. Priority Date: 04/02/2001
• Status: Active Grant

• Current Assignee: Polaris Innovations Limited (Wi-LAN Inc.)
• Original Assignee: Infineon Technologies AG
• Inventors: Rein, Achim, Frerichs, Martin
• Granted Patent: US 6,865,727 B2
• Time in Patent Office: Days
• US Class Current: 716/4
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347

Abstract

A method for verifying a layout of an integrated circuit with the aid of a computer and the fabrication of the circuit applying the method includes the steps of inserting several floating structures, namely fill structures, in a layout wiring plane, configuring the structures into structural regions, taking the regions into consideration with respect to the wiring capacities in the vicinity of these structures for a low computational outlay, and, for each structural region (3), defining a boundary polynomial that is modeled according to the outer margins of the structural region. In the calculation of the capacity coefficient, a structural region can be taken into consideration as a whole by a large filler polygon.

Claims

1. A method for calculating the capacity of an integrated circuit layout, which comprises:

providing an integrated circuit layout with wiring planes and at least one wiring network;

providing floating structures in at least one structural region in at least one wiring plane, the structural region having an outer margin and being separated from the wiring network in the wiring plane;

defining a boundary polygon for the structural region, the boundary polygon having a shape modeled according to the outer margin of the structural region;

calculating a capacity coefficient for the structural region with the floating structures based upon a filler polygon corresponding to the boundary polygon; and

utilizing the capacity coefficient computed for the structural region with the floating structures for a capacity extraction of the integrated circuit layout.

2. The method according to claim 1, which further comprises:

modeling the filler polygon with an isolator polygon having a high relative permittivity and equal dimensions; and

calculating the capacity coefficient for the structural region with the floating structures with a model in which the isolator polygon is completely removed to add a standard isolator, having a thickness reduced by a thickness of the isolator polygon, in a region of the structural region as the capacity coefficient of two wiring planes between which is disposed the wiring plane with the floating structures.

3. The method for fabricating an integrated circuit with the method according to claim 1, which further comprises:

comparing the capacity calculated based upon the capacity extraction to the circuit configuration and optimizing the layout if a discrepancy exists; and

generating a mask set for fabricating the integrated circuit based upon the optimized layout.

4. The method for fabricating an integrated circuit with the method according to claim 2, which further comprises:

comparing the capacity calculated based upon the capacity extraction to the circuit configuration and optimizing the layout if a discrepancy exists; and

generating a mask set for fabricating the integrated circuit based upon the optimized layout.

5. The method according to claim 1, wherein the floating structures are fill structures.

6. A method for fabricating an integrated circuit, which comprises:

providing an integrated circuit layout with wiring planes and at least one wiring network;

providing floating structures in at least one structural region in at least one wiring plane, the structural region having an outer margin and being separated from the wiring network in the wiring plane;

defining a boundary polygon for the structural region, the boundary polygon having a shape modeled according to the outer margin of the structural region;

calculating a capacity coefficient for the structural region with the floating structures based upon a filler polygon corresponding to the boundary polygon;

utilizing the capacity coefficient computed for the structural region with the floating structures for a capacity extraction of the integrated circuit layout;

comparing the capacity calculated based upon the capacity extraction to the circuit configuration and optimizing the layout if a discrepancy exists; and

generating a mask set for fabricating the integrated circuit based upon the optimized layout.

7. The method according to claim 6, wherein the floating structures are fill structures.

8. A method for fabricating an integrated circuit, which comprises:

providing an integrated circuit layout with wiring planes and at least one wiring network;

providing floating structures in at least one structural region in at least one wiring plane, the structural region having an outer margin and being separated from the wiring network in the wiring plane;

defining a boundary polygon for the structural region, the boundary polygon having a shape modeled according to the outer margin of the structural region;

calculating a capacity coefficient for the structural region with the floating structures based upon a filler polygon corresponding to the boundary polygon and modeling the filler polygon with an isolator polygon having a high relative permittivity and equal dimensions;

calculating the capacity coefficient for the structural region with the floating structures with a model in which the isolator polygon is completely removed to add a standard isolator, having a thickness reduced by a thickness of the isolator polygon, in a region of the structural region as the capacity coefficient of two wiring planes between which is disposed the wiring plane with the floating structures;

utilizing the capacity coefficient computed for the structural region with the floating structures for a capacity extraction of the integrated circuit layout;

comparing the capacity calculated based upon the capacity extraction to the circuit configuration and optimizing the layout if a discrepancy exists; and

generating a mask set for fabricating the integrated circuit based upon the optimized layout.

9. The method according to claim 8, wherein the floating structures are fill structures.