System and method for correcting design rule violations in a mask layout file

• US 20020144230A1
• Filed: 05/31/2002
• Published: 10/03/2002
• Est. Priority Date: 09/22/1999
• Status: Abandoned Application

• Current Assignee: Toppan Photomasks Incorporated (TOPPAN Holdings, Inc.)
• Original Assignee: DuPont Displays Incorporated (Corteva, Inc.)
• Inventors: Rittman, Dan
• Application Number:
  US10/159,566
• Publication Number:
  US 20020144230A1
• Time in Patent Office: Days
• US Class Current: 716/19
• CPC Class Codes: G03F 1/36 Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

A system and method for correcting design rule violations in a mask layout file are disclosed. The method includes comparing a feature dimension in a mask layout file with a design rule in a technology file. If the feature dimension is less than the design rule, a design rule violation is identified and automatically corrected in the mask layout file.

Claims

1. An automated method for correcting design rule violations in a mask layout file, comprising:

comparing a feature dimension in a mask layout file with a design rule in a technology file;

identifying a design rule violation in the mask layout file if the feature dimension is less than the design rule; and

automatically correcting the design rule violation in the mask layout file.

2. The method of claim 1, further comprising measuring a distance between a first feature and a second feature to determine the feature dimension.

3. The method of claim 1, further comprising measuring a distance between a first edge and a second edge of a feature to determine the feature dimension.

4. The method of claim 1, further comprising:

determining if the feature dimension in the mask layout file is greater than the design rule in the technology file; and

modifying the feature dimension until the feature dimension is approximately equal to the design rule.

5. The method of claim 1, further comprising generating a clean mask layout file that does not include the design rule violation.

6. The method of claim 1, wherein automatically correcting the design rule violation in the mask layout file comprises adjusting the feature dimension until the feature dimension is approximately equal to or greater than the design rule.

7. The method of claim 1, further comprising generating an output file that includes the design rule violation.

8. The method of claim 1, wherein the mask layout file is hierarchical.

9. The method of claim 1, further comprising the mask layout file including first polygons that represent a first feature and second polygons that represent a second feature.

10. The method of claim 9, wherein automatically correcting the design rule violation in the mask layout file comprises repositioning edges of the first and second polygons in the mask layout file until the feature dimension is approximately equal to or greater than the design rule.

11. The method of claim 1, further comprising the feature dimension defining a space between three or more features.

12. The method of claim 1, further comprising the design rule selected from a group consisting of an n-well spacing, a p-well spacing, a diffusion spacing, a polysilicon spacing, a metal spacing and a contact spacing.

13. The method of claim 1, further comprising the design rule selected from a group consisting of a n-well width, a p-well width, a diffusion width, a polysilicon width, a metal width and a contact width.

15. The system of claim 14, further comprising the instructions operable to perform operations including measuring a space between a first feature and a second feature to determine the feature dimension.

16. The system of claim 14, further comprising the instructions operable to perform operations including measuring a width of a feature to determine the feature dimension.

17. The system of claim 14, further comprising the instructions operable to perform operations including:

determining if the feature dimension in the mask layout file is greater than the design rule in the technology file; and

modifying the feature dimension until the feature dimension is approximately equal to the design rule.

18. The system of claim 14, further comprising the instructions operable to perform operations including generating a clean mask layout file that does not include the design rule violation.

19. The system of claim 14, further comprising the instructions operable to perform operations including generating an output file that includes the design rule violation.

20. The system of claim 14, wherein automatically correcting the design rule violation in the mask layout file comprises adjusting the feature dimension until the feature dimension is approximately equal to or greater than the design rule.

21. The system of claim 14, further comprising the instructions operable to perform operations including:

identifying the design rule violation in one or more instances of a subcell in the mask layout file, the subcell located in a top-level cell; and

simultaneously correcting the design rule violation in each instance of the subcell.

14. A computer system for correcting design rule violations in a mask layout file, comprising:

a processing resource;

a computer readable memory; and

processing instructions encoded in the computer readable memory, the processing instructions, when executed by the processing resource, operable to perform operations comprising;

comparing a feature dimension in a mask layout file with a design rule in a technology file;

identifying a design rule violation in the mask layout file if the feature dimension is less than the design rule; and

automatically correcting the design rule violation in the mask layout file.

22. Software for correcting design rule violations in a mask layout file, the software being embodied in computer-readable media and when executed operable to:

compare a feature dimension in a mask layout file with a design rule in a technology file;

identify a design rule violation in the mask layout file if the feature dimension is less than the design rule; and

automatically correct the design rule violation in the mask layout file.

23. The software of claim 22, wherein the feature dimension comprises a space between a first polygon and a second polygon in the mask layout file.

24. The software of claim 22, wherein the feature dimension comprises a dimension associated with a polygon in the mask layout file.

25. The software of claim 22, further operable to correct the design rule violation in the mask layout file by adjusting the feature dimension until the feature dimension is approximately equal to or greater than the design rule.

26. The software of claim 22, further operable to:

determine if the feature dimension in the mask layout file is greater than the design rule in the technology file; and

modify the feature dimension until the feature dimension is approximately equal to the design rule.

27. The software of claim 22, further operable to generate a clean mask layout file that does not include the design rule violation.

28. The software of claim 22, wherein the mask layout file comprises a parent cell that includes one or more subcells.

29. The software of claim 28, further operable to:

compare the feature dimension in one subcell with the design rule in the technology file;

identify the design rule violation in the one subcell if the feature dimension is less than the design rule; and

simultaneously correct the design rule violation in each of the subcells.