Wiring substrate

• US 20020145197A1
• Filed: 03/22/2002
• Published: 10/10/2002
• Est. Priority Date: 03/23/2001
• Status: Active Grant

• Current Assignee: NGK Spark PLUG Company Limited
• Original Assignee: NGK Spark PLUG Company Limited
• Inventors: Kimura, Yukihiro, Tamaki, Mitsuru, Ohta, Sumio
• Granted Patent: US 7,102,085 B2
• Time in Patent Office: Days
• US Class Current: 257/734
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 23/49833 the chip support structure consisting of a plurality of insulating substrates
• CPC Class Codes: H01L 23/642 Capacitive arrangements H01L23/49589, H01L23/645, H01L23/647, H01L23/66 take precedence; capacitive effects between wiring layers on the semiconductor body H01L23/5222
• CPC Class Codes: H01L 24/81 using a bump connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/0103 Zinc [Zn]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01046 Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 Silver [Ag]
• CPC Class Codes: H01L 2924/0105 Tin [Sn]
• CPC Class Codes: H01L 2924/01051 : Antimony [Sb]
• CPC Class Codes: H01L 2924/01056 : Barium [Ba]
• CPC Class Codes: H01L 2924/01057 : Lanthanum [La]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/19106 : in a mirrored arrangement on two different side of a common die mounting substrate
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3511 : Warping
• CPC Class Codes: H05K 1/0231 : Capacitors or dielectric substances
• CPC Class Codes: H05K 1/186 : manufactured by mounting on or connecting to patterned circuits before or during embedding
• CPC Class Codes: H05K 3/4602 : characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated

Abstract

A wiring substrate is configured such that a build-up layer is formed only on a front surface (a single side) of a core substrate and such that the distance between a semiconductor device mounted on the front surface thereof and an electronic component mounted on the back surface thereof or incorporated therein behind the back surface is reduced to thereby enhance electrical characteristics of an electrically continuous path therebetween, and whose overall strength is enhanced so as not to be prone to deflection or warpage. The wiring substrate includes a relatively thin first core substrate 2 having a front surface 3 and a back surface 4; a relatively thick second core substrate 6 superposed on the back surface 4 of the first core substrate 2 and having a through opening 9 formed therein, the first substrate 2 and the through opening 9 defining a recess 9; and a build-up layer BU formed on the front surface 3 of the first core substrate 2 and including wiring layers 16 and 25 and dielectric layers 23 and 26.

Claims

1. A wiring substrate comprising:

a first core substrate having a front surface and a back surface;

a second core substrate superposed on the back surface of said first core substrate and having a through opening formed therein, the first substrate and the through opening defining a recess; and

a build-up layer formed on the front surface of said first core substrate and comprising a plurality of wiring layers and a plurality of dielectric layers.

2. The wiring substrate as claimed in claim 1, wherein said second core substrate having the through opening formed therein is thicker than said first core substrate.

3. The wiring substrate as claimed in claim 1, comprising a bonding layer and a wiring layer interposed between said first core substrate and said second core substrate having the through opening formed therein.

4. The wiring substrate as claimed in claim 1, wherein said first core substrate has a thickness of not less than 100 μ

m and not greater than 400 μ

m, and said second core substrate has a thickness of not less than 500 μ

m and not greater than 1000 μ

m.