An algorithm for finding vectors to stimulate all paths and arcs through an LVS gate

• US 20020145433A1
• Filed: 04/04/2001
• Published: 10/10/2002
• Est. Priority Date: 04/04/2001
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Stevens, Kenneth S., Morrise, Matthew C.
• Granted Patent: US 6,557,149 B2
• Time in Patent Office: Days
• US Class Current: 324/530
• CPC Class Codes: G01R 31/318357 Simulation computer simulation of digital circuits G06F30/3308
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking

Abstract

A method and system for characterizing and validating the timing of LVS circuits. In particular, based upon an input of a topological description of an LVS circuit (e.g., a netlist) and other circuit parameters such as a clock specification or any mutex or logical correlations between inputs and ignored devices, an output of all paths and arcs from primary inputs to sense amplifier inputs is generated. A complete set of valid input vectors required to exercise all paths is generated. These vectors may then be exhaustively simulated to provide input waveforms to all sense amplifiers.

Claims

1. A method for determining paths and arcs through an LVS (“

Low Voltage Differential Sense”

) circuit, the LVS circuit including at least one transistor and at least one sense amplifier, the method comprising;

(a) receiving a topological description of the LVS circuit;

(b) determining a function for each transistor in the LVS circuit as one of a drive transistor, a reset transistor and a pass transistor;

(c) determining at least one path from a transistor having a drive function to a sense amplifier; and

(d) for each path determining an associated arc vector.

2. The method according to claim 1, wherein part (b) includes analyzing LVS circuit characteristics information, the LVS circuit characteristics information specifying at least pre-charge information pertaining to the LVS circuit.

3. The method according to claim 2, wherein if the LVS circuit utilizes a high pre-charge scheme, p-MOS transistors coupled to power are characterized as drive transistors, transistors coupled to ground are characterized as reset transistors and transistors coupled to intermediate nodes are characterized as pass transistors.

4. The method according to claim 1, wherein part (c) includes performing a depth first search from each transistor characterized as a drive transistor to a sense amplifier.

5. The method according to claim 4, wherein part (c) further includes starting with a transistor characterized as a drive transistor recursively executing a transistor tracing process and a node tracing process until a sense amplifier is reached.

6. The method according to claim 5, wherein the transistor tracing process performs the following:

(i) receiving a current transistor;

(ii) if the current transistor is assigned a visited status, returning from the transistor tracing process;

(iii) associating the current transistor with a visited status;

(iv) setting a gate signal for the current transistor;

(v) storing the selected gate signal for the current transistor;

(vi) executing a node tracing process to trace to a source node of the current transistor;

(vii) executing the node tracing process to trace to a drain node of the current transistor;

(viii) disassociating the current transistor with a visited status; and

(ix) returning from the transistor tracing process.

7. The method according to claim 5, wherein the node tracing process performs the following:

(i) receiving a current node;

(ii) if the current node is coupled to a power source, ground, or a clock, returning from the node tracing process;

(iii) associating the current node with a visited status;

(iv)if the current node is coupled to a sense amplifier, determining a path as a function of at least one stored gate signal;

(v) executing the transistor tracing process for all transistors coupled to the current node;

(vi) disassociating the current node with a visited status; and

(vii) returning from the node tracing process.

8. The method according to claim 7, wherein part (d) includes determining at least one arc from a stored gate transistor to a sense amplifier.

9. A system for determining paths and arcs through an LVS (“

Low Voltage Differential Sense”

) circuit, the LVS circuit including at least one transistor and at least one sense amplifier, comprising;

a processor, wherein the processor is adapted to;

(a) receive a topological description of the LVS circuit;

(b) determine a function for each transistor in the LVS circuit as one of a drive transistor, a reset transistor and a pass transistor;

(c) determine at least one path from a transistor having a drive function to a sense amplifier; and

(d) for each path determine an associated arc vector.

10. The system according to claim 9, wherein the processor receives LVS circuit characteristics information, the LVS circuit characteristics information specifying at least pre-charge information pertaining to the LVS circuit.

11. The system according to claim 9, wherein the processor performs a depth first search from each transistor characterized as a drive transistor to a sense amplifier.

13. The medium storing instructions according to claim 12, wherein part (b) includes analyzing LVS circuit characteristics information, the LVS circuit characteristics information specifying at least pre-charge information pertaining to the LVS circuit.

14. The medium storing instructions according to claim 13, wherein if the LVS circuit utilizes a high pre-charge scheme, p-MOS transistors coupled to power are characterized as drive transistors, transistors coupled to ground are characterized as reset transistors and transistors coupled to intermediate nodes are characterized as pass transistors.

15. The medium storing instructions according to claim 12, wherein part (c) includes performing a depth first search from each transistor characterized as a drive transistor to a sense amplifier.

17. The method according to claim 16, wherein part (d) includes performing a depth first search from each transistor characterized as a drive transistor to a sense amplifier.

12. A medium storing instructions adapted to be executed by a processor to perform the following:

(a) receiving a topological description of an LVS circuit;

(b) determining a function for each transistor in the LVS circuit as one of a drive transistor, a reset transistor and a pass transistor;

(c) determining at least one path from a transistor having a drive function to a sense amplifier; and

(d) for each path determining an associated arc vector.

16. A method for determining paths and arcs through an LVS (“

Low Voltage Differential Sense”

) circuit, the LVS circuit including at least one transistor, at least one node, and at least one sense amplifier, the method comprising;

(a) receiving a topological description of the LVS circuit;

(b) receiving information pertaining to at least one of a mutex and a logical correlation corresponding to at least one node in the LVS circuit;

(c) determining a function for each transistor in the LVS circuit as one of a drive transistor, a reset transistor and a pass transistor;

(d) determining at least one path from a transistor having a drive function to a sense amplifier as a function of the information pertaining to the at least one of the mutex and the logical correlation; and

(e) for each path determining an associated arc vector.