MULTI-LINK SEGMENTATION AND REASSEMBLY FOR BONDING MULTIPLE PVC'S IN AN INVERSE MULTIPLEXING ARRANGEMENT
First Claim
1. A method, comprising:
- generating a plurality of multilink segmentation and reassembly sublayer cells at a first location;
distributing the plurality of multilink segmentation and reassembly sublayer cells across a plurality of virtual circuits;
transmitting the plurality of multilink segmentation and reassembly sublayer cells to a second location via the plurality of virtual circuits; and
receiving the plurality of multilink segmentation and reassembly sublayer cells at the second location.
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Accused Products
Abstract
Systems and methods are described for multi-link segmentation and reassembly for bonging multiple virtual circuits in an inverse multiplexing arrangement. A method includes: generating a plurality of multilink segmentation and reassembly sublayer cells at a first location; distributing the plurality of multilink segmentation and reassembly sublayer cells across a plurality of virtual circuits; transmitting the plurality of multilink segmentation and reassembly sublayer cells to a second location via the plurality of virtual circuits; and receiving the plurality of multilink segmentation and reassembly sublayer cells at the second location. An apparatus includes a multilink segmentation and reassembly sublayer transmitter, including: a source buffer; a multilink controller coupled to the source buffer; and a plurality of virtual circuits coupled to the multilink controller.
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Citations
46 Claims
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1. A method, comprising:
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generating a plurality of multilink segmentation and reassembly sublayer cells at a first location;
distributing the plurality of multilink segmentation and reassembly sublayer cells across a plurality of virtual circuits;
transmitting the plurality of multilink segmentation and reassembly sublayer cells to a second location via the plurality of virtual circuits; and
receiving the plurality of multilink segmentation and reassembly sublayer cells at the second location. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25, 26, 27, 28, 29, 30, 31, 32, 33, 35, 36, 37, 38, 39)
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14. A method, comprising converting a cell into a multilink segmentation and reassembly sublayer format, including:
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receiving an asymmetric transfer mode network cell from a conventional segmentation and reassembly sublayer mechanism;
writing the asymmetric transfer mode network cell to a memory buffer;
reading a plurality of octets from the memory buffer;
appending a multilink segmentation and reassembly sublayer identifier and a multilink segmentation and reassembly sublayer sequence number to the plurality of octets forming a multilink segmentation and reassembly sublayer cell;
transmitting the multilink segmentation and reassembly sublayer cell to a virtual circuit controller;
appending a plurality of header octets to the multilink segmentation and reassembly sublayer cell; and
transmitting the multilink segmentation and reassembly sublayer cell via a virtual circuit.
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24. A method, comprising converting plurality of multilink segmentation and reassembly sublayer cells into an asymmetric transfer mode format, including:
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receiving a plurality multilink segmentation and reassembly sublayer cells from a plurality of virtual circuits;
writing the plurality of multilink segmentation and reassembly sublayer cells to a memory buffer in a sequence defined by a plurality of multilink segmentation and reassembly sublayer sequence numbers;
reading a plurality of octets from the memory buffer;
assembling the plurality of octets into a plurality of asymmetric transfer mode cells; and
transmitting the plurality of asymmetric transfer mode cells to a conventional segmentation and reassembly sublayer mechanism.
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34. An apparatus, comprising a multilink segmentation and reassembly sublayer transmitter, including:
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a source buffer;
a multilink controller coupled to the source buffer; and
a plurality of virtual circuits coupled to the multilink controller.
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40. An apparatus, comprising a multilink segmentation and reassembly sublayer receiver, including:
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a plurality of virtual circuits;
a multilink controller coupled to the plurality of virtual circuits;
a plurality of intermediate buffers coupled to the multilink controller; and
a receive buffer coupled to the plurality of intermediate buffers. - View Dependent Claims (41, 42, 43, 44, 46)
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45. An apparatus, comprising a segmentation and reassembly sublayer converter, including:
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a segmentation and reassembly sublayer mechanism;
a memory write controller coupled to the segmentation and reassembly sublayer mechanism;
a memory buffer coupled to the memory write controller;
a memory read controller coupled to the memory buffer; and
a virtual circuit controller coupled to the memory read controller.
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Specification