Method and system to accelerate cryptographic functions for secure e-commerce applications

• US 20020146128A1
• Filed: 04/05/2001
• Published: 10/10/2002
• Est. Priority Date: 12/19/2000
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Mauro, Anthony P., Willkie, James J.
• Granted Patent: US 7,305,092 B2
• Time in Patent Office: Days
• US Class Current: 380/270
• CPC Class Codes: G06F 21/00 Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
• CPC Class Codes: H04L 2209/56 Financial cryptography, e.g. electronic payment or e-cash
• CPC Class Codes: H04L 2463/102 applying security measure for e-commerce data processing systems or methods, specially adapted for e-commerce G06Q30/00
• CPC Class Codes: H04L 63/0485 Networking architectures for enhanced packet encryption processing, e.g. offloading of IPsec packet processing or efficient security association look-up
• CPC Class Codes: H04L 63/08 for authentication of entities cryptographic mechanisms or cryptographic arrangements for entity authentication H04L9/32
• CPC Class Codes: H04L 63/12 Applying verification of the received information cryptographic mechanisms or cryptographic arrangements for data integrity or data verification H04L9/32
• CPC Class Codes: H04L 63/166 at the transport layer
• CPC Class Codes: H04L 67/04 specially adapted for terminals or networks with limited capabilities; specially adapted for terminal portability
• CPC Class Codes: H04L 69/12 Protocol engines
• CPC Class Codes: H04L 69/32 Architecture of open systems interconnection [OSI] 7-layer type protocol stacks, e.g. the interfaces between the data link level and the physical level
• CPC Class Codes: H04L 9/40 Network security protocols

Abstract

A device and method for accelerating functioning of a software application having multi-layer, high overhead protocols, wherein the device has a processor (12) operating a software application (20) having a multi-layer protocol; a high performance processor (14) configured to operate at least one layer of the multi-layer protocol; and a memory (16) accessible to each of the processor (12) and the high performance processor (14).

Claims

1. A device for accelerating functioning of a software application having multi-layer, high overhead protocols, the device comprising:

a first processor operating a software application having a multi-layer protocol;

a high performance processor configured to operate one layer of the multi-layer protocol according to a command from the first processor; and

a memory accessible to each of the first processor and the high performance processor for passing commands and data between the first processor and the high performance processor.

2. The device of claim 1 wherein the first processor operates a multi-layer security protocol.

3. The device of claim 1 wherein the high performance processor is configured to operate a mathematical algorithm layer of the multi-layer protocol.

4. The device of claim 1 wherein the high performance processor further comprises a digital signal processor.

5. The device of claim 4 wherein the digital signal processor is further configured to operate a modular math function.

6. The device of claim 5 wherein the digital signal processor is further configured to operate a modular math function comprising an exponentiation function.

7. A device for accelerating security protocols, the device comprising:

a multi-layer security protocol having one or more of an encryption algorithm and an authentication algorithm;

a shared memory;

a processor coupled to the memory and operating a first portion of a predetermined one of the security protocols; and

a high performance processor coupled to the memory and operating a second portion of the predetermined one of the security protocols.

8. The device of claim 7 wherein the high performance processor operates the second portion of the security protocol in response to a command from the processor and returns an interrupt signal.

9. The device of claim 7 wherein the high performance processor operates the second portion of the security protocol on data from the processor.

10. The device of claim 9 wherein the high performance processor operates the second portion of the security protocol using a modular math function.

11. The device of claim 10 wherein the processor passes the data to the high performance processor via the shared memory, and the high performance processor returns a result from operating the second portion of the security protocol to the processor via the shared memory.

13. The circuit of claim 12 wherein the first and second processor cores are coupled together through the shared memory.

14. The circuit of claim 12 wherein the security services protocol further comprises one of an encryption algorithm and an authentication algorithm.

16. The method of claim 15 wherein performing the distributed function further comprises performing the distributed function in response to a command from a first processor.

17. The method of claim 16 wherein the first processor performs the partitioning of the function.

18. The method of claim 15 wherein performing the distributed function further comprises operating an algorithm to perform the function.

19. The method of claim 18 wherein the algorithm is a modular math function.

20. The method of claim 15 wherein the multi-layer protocol is a security protocol.

12. A circuit for partitioning a multi-layer security services protocol, the circuit comprising:

a shared memory;

first and second processor cores coupled to the shared memory;

a multi-layer security services protocol partitioned between each of the first and second processor cores;

one or more application program interfaces operated by the first processor core for interfacing between the security services protocol and the second processor core; and

a modular math function operating on the second processor core.

15. A method for accelerating a multi-layer protocol, the method comprising:

partitioning a function of a multi-layer protocol in a first processor;

distributing the function to a second high performance processor via a memory shared by both the first and second processors;

performing the distributed function in the high performance processor; and

returning a result of the distributed function from the high performance processor via the shared memory.