Semiconductor device and method of manufacturing the same

• US 20020146864A1
• Filed: 04/04/2002
• Published: 10/10/2002
• Est. Priority Date: 04/04/2001
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Suzuki, Kazunari, Suzuki, Hiromichi, Nishi, Kunihiko, Miyaki, Yoshinori
• Granted Patent: US 6,960,823 B2
• Time in Patent Office: Days
• US Class Current: 438/123
• CPC Class Codes: H01L 2224/2612 Auxiliary members for layer connectors, e.g. spacers
• CPC Class Codes: H01L 2224/29007 Layer connector smaller than the underlying bonding area
• CPC Class Codes: H01L 2224/29109 Indium [In] as principal constituent
• CPC Class Codes: H01L 2224/29111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/29139 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/2919 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/32014 the layer connector being smaller than the bonding area, e.g. bond pad
• CPC Class Codes: H01L 2224/32055 being circular or elliptic
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/48639 Silver (Ag) as principal constituent
• CPC Class Codes: H01L 2224/48664 Palladium (Pd) as principal constituent
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/78301 Capillary
• CPC Class Codes: H01L 2224/78983 of the mounting surface
• CPC Class Codes: H01L 2224/8319 : Arrangement of the layer connectors prior to mounting
• CPC Class Codes: H01L 2224/838 : Bonding techniques
• CPC Class Codes: H01L 2224/85181 : connecting first on the semiconductor or solid-state body, i.e. on-chip, regular stitch
• CPC Class Codes: H01L 2224/85439 : Silver (Ag) as principal constituent
• CPC Class Codes: H01L 2224/85464 : Palladium (Pd) as principal constituent
• CPC Class Codes: H01L 2224/92 : Specific sequence of method steps
• CPC Class Codes: H01L 2224/92247 : the second connecting process involving a wire connector
• CPC Class Codes: H01L 23/49503 : characterised by the die pad
• CPC Class Codes: H01L 23/49513 : having bonding material between chip and die pad
• CPC Class Codes: H01L 23/49541 : Geometry of the lead-frame
• CPC Class Codes: H01L 23/49582 : Metallic layers on lead frames
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/78 : Apparatus for connecting with wire connectors
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01026 : Iron [Fe]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/0103 : Zinc [Zn]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01051 : Antimony [Sb]
• CPC Class Codes: H01L 2924/01057 : Lanthanum [La]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01083 : Bismuth [Bi]
• CPC Class Codes: H01L 2924/0132 : Binary Alloys
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/0133 : Ternary Alloys
• CPC Class Codes: H01L 2924/0134 : Quaternary Alloys
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/0665 : Epoxy resin
• CPC Class Codes: H01L 2924/078 : Adhesive characteristics other than chemical
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15738 : the principal constituent melting at a temperature of greater than or equal to 950 C and less than 1550 C
• CPC Class Codes: H01L 2924/15747 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2924/1576 : Iron [Fe] as principal constituent
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/20753 : larger or equal to 30 microns less than 40 microns
• CPC Class Codes: H01L 2924/3512 : Cracking

Abstract

To improve a reflow characteristic and realize leadlessness. A semiconductor device comprises a cross die pad which supports a semiconductor chip and in which an area of the region joined to the semiconductor chip is smaller than that of the outer size thereof being smaller than the rear surface of the semiconductor chip; wires connected to pads of the semiconductor chip; a plurality of inner leads which are arranged around the semiconductor chip and in which a silver plating layer is formed at a wire bonding area; molding resin for resin sealing the semiconductor chip; a plurality of outer leads exposed from the molding resin and in which a lead-free metallic layer is formed on a contact surface, wherein the flat surface size of the molding resin is formed to be equal to or less than 28 mm×28 mm and the thickness thereof is formed to be 1.4 mm or less, and thereby it is possible to improve a reflow characteristic and realize leadlessness.

Claims

1. A semiconductor device comprising:

a die pad supporting a semiconductor chip and being smaller in outer size than the surface opposite to the semiconductor die surface of said semiconductor chip;

a wire connected to a surface electrode of said semiconductor chip;

a plurality of inner leads expanding around said semiconductor chip, in which a silver plating layer is formed at a wire bonding area to which said wire is joined;

a molding resin for resin sealing said semiconductor chip; and

a plurality of outer leads connected to said inner leads and protruding from said molding resin, in which a lead-free metallic layer is formed on a contact surface,

wherein said semiconductor device is one of an LQFP and a TQFP in which the flat surface size of said molding resin is formed to be equal to or less than 28 mm×

28 mm.

9. The semiconductor device according to claim 1,

wherein said lead-free metallic layer is a solder plating layer having a fusion point higher than tin-lead eutectic solder.

2. A semiconductor device comprising:

a die pad supporting a semiconductor chip and being smaller in outer size than the surface opposite to the semiconductor die surface of said semiconductor chip;

a wire connected to a surface electrode of said semiconductor chip;

a plurality of inner leads expanding around said semiconductor chip, in which a silver plating layer is formed at a wire bonding area to which said wire is joined;

a molding resin for resin sealing said semiconductor chip; and

a plurality of outer leads connected to the inner leads and protruding from the molding resin, in which a lead-free metallic layer is formed on a contact surface,

wherein said semiconductor device is a QFP in which the flat surface size of said molding resin is formed to be equal to or less than 28 mm×

28 mm and the thickness thereof is formed to be 1.4 mm or less.

3. A semiconductor device comprising:

a cross die pad supporting a semiconductor chip and being smaller in outer size than the surface opposite to the semiconductor die surface of said semiconductor chip;

a wire connected to a surface electrode of said semiconductor chip;

a plurality of inner leads expanding around said semiconductor chip, in which a silver plating layer is formed at a wire bonding area to which said wire is joined;

a molding resin for resin sealing said semiconductor chip; and

a plurality of outer leads connected to said inner leads and protruding from said molding resin, in which a lead-free metallic layer is formed on a contact surface,

wherein said semiconductor device is one of an LQFP and a TQFP in which the flat surface size of said molding resin is formed to be equal to or less than 28 mm×

28 mm.

4. A semiconductor device comprising:

a cross die pad supporting a semiconductor chip and being smaller in outer size than the surface opposite to the semiconductor die surface of said semiconductor chip;

wires connecting to surface electrodes of the semiconductor chip;

a plurality of inner leads expanding around said semiconductor chip, in which a silver plating layer is formed at a wire bonding area to which said wire is joined;

molding resin for resin sealing said semiconductor chip; and

a plurality of outer leads connected to said inner leads and protruding from said molding resin, in which a lead-free metallic layer is formed on a contact surface,

wherein said semiconductor device is a QFP in which the flat surface size of said molding resin is formed to be equal to or less than 28 mm×

28 mm and the thickness thereof is formed to be 1.4 mm or less.

5. A semiconductor device comprising:

a die pad supporting a semiconductor chip and being smaller in outer size than the surface opposite to the semiconductor die surface of said semiconductor chip;

a wire connecting to a surface electrode of said semiconductor chip;

a plurality of inner leads expanding around said semiconductor chip, in which a silver plating layer is formed at a wire bonding area to which said wire is joined;

molding resin for resin sealing said semiconductor chip; and

a plurality of outer leads connected to said inner leads and protruding from said molding resin, in which a lead-free metallic layer is formed on a contact surface,

wherein said semiconductor device is one of a QFP, an LQFP and a TQFP, the QFP being formed such that the flat surface size of said molding resin is formed to be equal to or less than 20 mm×

20 mm and the thickness thereof is formed to be 3 mm or less, and the LQFP and the TQFP being formed respectively such that the flat surface size of said molding resin is formed to be equal to or less than 20 mm×

20 mm.

10. The semiconductor device according to claim 5,

wherein a double-sided adhesive tape is provided as a die bonding material for fixing said semiconductor chip to one of said die pad and said cross die pad.

6. A semiconductor device comprising:

a cross die pad supporting a semiconductor chip and being smaller in outer size than the surface opposite to the semiconductor die surface of said semiconductor chip;

a wire connecting to a surface electrode of said semiconductor chip;

a plurality of inner leads expanding around said semiconductor chip, in which a silver plating layer is formed at a wire bonding area to which said wire is joined;

molding resin for resin sealing said semiconductor chip; and

a plurality of outer leads connected to said inner leads and protruding from said molding resin, in which a lead-free metallic layer is formed on a contact surface,

wherein said semiconductor device is one of a QFP, an LQFP and a TQFP, the QFP being formed such that the flat surface size of said molding resin is formed to be equal to or less than 20 mm×

20 mm and the thickness thereof is formed to be 3 mm or less, and the LQFP and the TQFP being formed respectively such that the flat surface size of said molding resin is formed to be equal to or less than 20 mm×

20 mm.

7. A semiconductor device comprising a QFN, said QFN including:

a die pad supporting a semiconductor chip and being smaller in outer size than the surface opposite to the semiconductor die surface of said semiconductor chip;

a wire connected to a surface electrode of said semiconductor chip;

a plurality of inner leads arranged around said semiconductor chip, in which a silver plating layer is formed at a wire bonding area to which said wire is joined;

molding resin for resin sealing said semiconductor chip; and

a plurality of outer leads arranged to be exposed to a circumferential portion of a surface located in a packaging side of said molding resin, in which a lead-free metallic layer is formed on a contact surface.

11. The semiconductor device according to claim 7,

wherein an adhesive tape and molding resin paste to be laminated thereon are provided as a die bonding material for fixing said semiconductor chip to one of said die pad and said cross die pad.

8. A semiconductor device comprising a QFN, said QFN including:

a cross die pad supporting a semiconductor chip and being smaller in outer size than the surface opposite to the semiconductor die surface of said semiconductor chip;

a wire connecting to a surface electrode of said semiconductor chip;

a plurality of inner leads arranged around said semiconductor chip, in which a silver plating layer is formed at wire bonding area to which said wire is joined;

molding resin for resin sealing said semiconductor chip; and

a plurality of outer leads arranged to be exposed to a circumferential portion of a surface located in a packaging side of said molding resin, in which a lead-free metallic layer is formed on a contact surface.

12. A method of manufacturing a semiconductor device, comprising the steps of:

preparing a lead frame having a die pad smaller in outer size than the surface opposite to the semiconductor die surface of a semiconductor chip, a plurality of inner leads in which a silver plating layer is formed on a wire bonding area, and a plurality of outer leads which are connected to said respective inner leads and in which a lead-free metallic layer is formed on a contact surface;

mounting said semiconductor chip onto said die pad via a die bonding material;

connecting, by a wire, a surface electrode of said semiconductor chip and said silver plating layer of said wire bonding area in said inner leads corresponding to the surface electrode;

forming molding resin by resin molding said semiconductor chip such that said plurality of outer leads protrude in which said lead-free metallic layer is formed on the contact surface; and

separating said plurality outer leads protruding from said molding resin, from a frame portion of said lead frame,

wherein the flat surface size of said molding resin is formed to be equal to or less than 28 mm×

28 mm, and thereby one of an LQFP and a TQFP is assembled.

13. A method of manufacturing a semiconductor device, comprising the steps of:

preparing a lead frame having a cross die pad smaller in outer size than the surface opposite to the semiconductor die surface of a semiconductor chip, a plurality of inner leads in which a silver plating layer is formed on a wire bonding area, and a plurality of outer leads which are connected to said respective inner leads and in which a lead-free metallic layer is formed on a contact surface;

mounting said semiconductor chip onto said die pad via a die bonding material;

connecting, by a wire, a surface electrode of said semiconductor chip and said silver plating layer of said wire bonding area in said inner leads corresponding to the surface electrode;

forming molding resin by resin molding said semiconductor chip such that said plurality of outer leads protrude in which said lead-free metallic layer is formed on the contact surface; and

separating said plurality of outer leads protruding from said molding resin, from a frame portion of said lead frame,

wherein the flat surface size of said molding resin is formed to be equal to or less than 28 mm×

28 mm, and thereby one of an LQFP and a TQFP is assembled.

14. A method of manufacturing a semiconductor device, comprising the steps of:

preparing a lead frame having a die pad smaller in outer size than the surface opposite to the semiconductor die surface of a semiconductor chip, a plurality of inner lead portions in which a silver plating layer is formed at a wire bonding area, and a plurality of outer lead portions in which a lead-free metallic layer is formed on a contact surface continuing on said inner lead portions;

mounting said semiconductor chip onto said die pad via a die bonding material;

connecting, by a wire, a surface electrode of said semiconductor chip and said silver plating layer of said wire bonding area in said inner lead portions corresponding to the surface electrode;

forming molding resin by resin molding said semiconductor chip such that said lead-free metallic layer of each of said plurality of outer lead portions is exposed to a circumferential portion thereof; and

separating said plurality of outer lead portions from a frame portion of said lead frame,

wherein a QFN is assembled.

15. A method of manufacturing a semiconductor device, comprising the steps of:

preparing a lead frame having a die pad smaller in outer size than the surface opposite to the semiconductor die surface of a semiconductor chip, a plurality of inner leads in which a silver plating layer is formed at a wire bonding area, and a plurality of outer leads connected to said respective inner leads;

mounting said semiconductor chip onto said die pad via a die bonding material;

connecting, by a wire, a surface electrode of said semiconductor chip and said silver plating layer of said wire bonding area in said inner leads corresponding to the surface electrode;

forming molding resin by resin molding said semiconductor chip such that said plurality of outer leads protrude;

forming a lead-free metallic layer on a contact surface of said plurality of outer leads protruding from said molding resin; and

separating said plurality of outer leads from a frame portion of said lead frame,

wherein the flat surface size of said molding resin is formed to be equal to or less than 28 mm×

28 mm, and thereby one of an LQFP and a TQFP is assembled.

16. A method of manufacturing a semiconductor device, comprising the steps of:

preparing a lead frame having a die pad smaller in outer size than the surface opposite to the semiconductor die surface of a semiconductor chip, a plurality of inner leads in which a silver plating layer is formed at a wire bonding area, and a plurality of outer leads connected to said inner leads;

mounting said semiconductor chip onto said die pad via a die bonding material;

connecting, by a wire, a surface electrodes of said semiconductor chip and said silver plating layer of said wire bonding area in said inner leads corresponding to the surface electrode;

forming molding resin by resin molding said semiconductor chip such that said plurality of outer leads protrude;

forming a lead-free metallic layer on a contact surface of each of said plurality of outer leads protruding from said molding resin; and

separating said plurality of outer leads from a frame portion of said lead frame;

wherein one of a QFP, an LQFP and a TQFP is assembled, the QFP being formed such that the flat surface size of said molding resin is equal to or less than 20 mm×

20 mm and the thickness thereof is 3 mm or less, and the LQFP and the TQFP being formed respectively such that the flat surface size of said molding resin is equal to or less than 20 mm×

20 mm.

17. A method of manufacturing a semiconductor device, comprising the steps of:

preparing a lead frame having a die pad smaller in outer size than the surface opposite to the semiconductor die surface of a semiconductor chip, a plurality of inner lead portions in which a silver plating layer is formed at wire bonding area, and a plurality of outer lead portions connected to said inner leads;

mounting said semiconductor chip onto said die pad via a die bonding material;

connecting, by a wire, a surface electrode of said semiconductor chip and said silver plating layer of said wire bonding area in said inner lead portions corresponding to the surface electrode;

forming molding resin by resin molding said semiconductor chip such that said plurality of outer lead portions is exposed to a circumferential portion of a surface located in a packaging side;

forming a lead-free metallic layer on the contact surface of said plurality of outer lead portions exposed to said molding resin; and

separating said plurality of outer lead portions from a frame portion of said lead frame,

wherein a QFN is assembled.

18. A method of manufacturing a semiconductor device, comprising the steps of:

preparing a lead frame having a cross die pad smaller in outer size than the surface opposite to the semiconductor die surface of a semiconductor chip, a plurality of inner leads in which a silver plating layer is formed at a wire bonding area, and a plurality of outer leads connected to said respective inner leads;

mounting said semiconductor chip onto said die pad via a die bonding material;

connecting, by a wire, a surface electrode of said semiconductor chip and said silver plating layer of said wire bonding area in said inner leads corresponding to the surface electrode;

forming molding resin by resin molding said semiconductor chip such that said plurality of outer leads protrude;

forming a lead-free metallic layer on each contact surface of said plurality of outer lead portions protruding from said molding resin; and

separating said plurality of outer leads from a frame portion of said lead frame,

wherein the flat surface size of said molding resin is formed to be equal to or less than 28 mm×

28 mm, and thereby one of an LQFP and a TQFP is assembled.

19. A method of manufacturing a semiconductor device, comprising the steps of:

preparing a lead frame having a cross die pad smaller in outer size than the surface opposite to the semiconductor die surface of a semiconductor chip, a plurality of inner leads in which a silver plating layer is formed at a wire bonding area, and a plurality of outer leads connected to said respective inner leads;

mounting said semiconductor chip onto said cross die pad via a die bonding material;

connecting, by a wire, a surface electrode of said semiconductor chip and said silver plating layer of said wire bonding area in said inner leads corresponding to the surface electrode;

forming molding resin by resin molding said semiconductor chip such that said plurality of outer leads protruded;

forming a lead-free metallic layer on each contact surface of said plurality outer lead portions protruding from said molding resin; and

separating said plurality of outer leads from a frame portion of said lead frame,

wherein one of a QFP, an LQFP and a TQFP is assembled, the QFP being formed such that the flat surface size of said molding resin is equal to or less than 20 mm×

20 mm and the thickness thereof is 3 mm or less, and the LQFP and the TQFP being formed respectively such that the flat surface size of said molding resin is equal to or less than 20 mm×

20 mm.

20. A method of manufacturing a semiconductor device, comprising the steps of:

preparing a lead frame having a cross die pad smaller in outer size than the surface opposite to the semiconductor die surface of a semiconductor chip, a plurality of inner lead portions in which a silver plating layer is formed at a wire bonding area, and a plurality of outer lead portions connected to said inner lead portions;

mounting said semiconductor chip onto said cross die pad via a die bonding material;

connecting, by a wire, a surface electrodes of said semiconductor chip and said silver plating layer of said wire bonding area in said inner lead portions corresponding to the surface electrode;

forming molding resin by resin molding said semiconductor chip such that said plurality of outer lead portions are exposed to a circumferential portion of a surface located in a packaging side;

forming a lead-free metallic layer on each contact surface of said plurality of outer lead portions exposed to said molding resin; and

separating said plurality of outer lead portions from a frame portion of said lead frame,

wherein a QFN is assembled.