Diagnosis of combinational logic circuit failures

• US 20020147952A1
• Filed: 04/06/2001
• Published: 10/10/2002
• Est. Priority Date: 04/06/2001
• Status: Active Grant

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: International Business Machines Corporation
• Inventors: Huisman, Leendert M., Heaberlin, Douglas C., Bartenstein, Thomas W.
• Granted Patent: US 6,721,914 B2
• Time in Patent Office: Days
• US Class Current: 714/734
• CPC Class Codes: G01R 31/317 Testing of digital circuits

Abstract

A method for diagnosing defects in an integrated circuit comprising: providing a set of failing test patterns; for each failing test pattern in the set of test patterns determining if a single stuck-at fault could cause the failing test pattern and determining a node on which a defect causing the single stuck-at fault could reside; selecting those failing test patterns that could be caused by a single stuck-at fault; and for those selected failing test patterns determining a first set of sets of nodes, such that each of the selected failing test patterns could be caused by a stuck-at zero or a stuck-at one on at least one node from each set of nodes from the first set of sets of nodes.

Claims

1. A method for diagnosing defects in an integrated circuit comprising:

providing a set of failing test patterns;

for each failing test pattern in said set of test patterns determining if a single stuck-at fault could cause said failing test pattern and determining a node on which a defect causing said single stuck-at fault could reside;

selecting those failing test patterns that could be caused by a single stuck-at fault; and

for those selected failing test patterns determining a first set of sets of nodes, such that each of said selected failing test patterns could be caused by a stuck-at zero or a stuck-at one on at least one node from each set of nodes from said first set of sets of nodes.

2. The method of claim 1, wherein determining if a single stuck-at fault could cause said failing test pattern includes:

selecting a test pattern from said set of failing test patterns;

creating one or more single-stuck at fault target faults;

simulating each said target fault against a fault machine to generate simulated fail patterns; and

determining if any said simulated fail patterns matches said selected test pattern.

3. The method of claim 2, wherein creating said target faults includes performing a trace back starting from a failing logic block output and terminating at a previous latch.

4.he. The method of claim 1, wherein determining said first set of sets of nodes further includes:

determining the size of each of said sets of nodes;

determining a set of minimal sets of nodes, said minimal sets of nodes having a minimal size; and

discarding all sets of nodes having a size higher than said minimal set size.

6. The method of claim 1, further comprising testing said integrated circuit to obtain said set of failing test patterns.

5. The method of claim 4, further comprising:

determining whether there is a second set of sets of nodes such that each minimal set of said set of minimal sets of nodes corresponds to a set of nodes obtained by taking one node from each set of nodes from said second set of sets of nodes and such that each set of nodes obtained by taking one node from each set of nodes from said second set of sets of nodes corresponds to one minimal set of nodes from said set of minimal sets of nodes.

7. A method for diagnosing defects in an integrated circuit comprising:

(a) providing a set of failing test patterns and a set of main faults;

(b) selecting a failing test pattern from said set of failing patterns;

(c) creating one or more single-stuck at fault target faults and adding said target faults to a set of target faults;

(d) selecting a target fault from said set of target faults;

(e) simulating said selected target fault against a fault machine to create a simulated fail pattern;

(f) comparing said simulated fail pattern to said selected fail pattern;

(g) if said simulated fail pattern matches said selected failing pattern, adding said selected target fault to a explaining node list otherwise going to step (h);

(h) repeating steps (d) through (g) until all target faults in said set of target faults have been selected;

(i) repeating steps (b) through (h) until all failing test patterns in said set of failing test patterns have been selected;

(j) selecting in turn, each simulated fault from said fault list, determining the associated nodes and creating sets of nodes; and

(k) selecting a first set of sets of nodes such that each said simulated fail pattern matching a selected failing pattern could be caused by a stuck-at zero or a stuck-at one on at least one node from each set of nodes from said first set of sets of nodes.

8. The method of claim 7, where said set of main faults is generated from a logic design corresponding to said integrated circuit.

9. The method of claim 7, wherein creating one or more single-stuck at fault target faults includes performing a trace back starting from a failing logic block output and terminating at a previous logic block.

10. The method of claim 7, wherein determining said first set of said sets of nodes further includes:

determining the size of each of said sets of nodes;

determining a set of minimal sets of nodes, said minimal sets of nodes having a minimal size; and

discarding all sets of nodes having a size higher than said minimal set size.

11. The method of claim 10, further comprising:

determining whether there is a second set of sets of nodes such that each minimal set of said set of minimal sets of nodes corresponds to a set of nodes obtained by taking one node from each set of nodes from said second set of sets of nodes and such that each set of nodes obtained by taking one node from each set of nodes from said second set of sets of nodes corresponds to one minimal set of nodes from said set of minimal sets of nodes.

12. The method of claim 7, further comprising testing said integrated circuit to obtain said set of failing test patterns.