Power saving integrated circuit and method of controlling the same

• US 20020149353A1
• Filed: 04/02/2002
• Published: 10/17/2002
• Est. Priority Date: 04/12/2001
• Status: Active Grant

• Current Assignee: LAPIS Semiconductor Co., Ltd. (ROHM Co., Ltd.)
• Original Assignee: OKI Electric Industry Company Limited
• Inventors: Inaba, Soichiro
• Granted Patent: US 6,713,994 B2
• Time in Patent Office: Days
• US Class Current: 323/283
• CPC Class Codes: G06F 1/24 Resetting means
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

An operating condition of an operating circuit is provided it to a register, a counter is set in accordance with an operating condition signal stored in the register, and the counter outputs a reset signal to the operating circuit. The operating condition signal indicates a reset delay period which is equal to the sum of a shortest rise time of power supply voltage and a reset period to reset the counter after the power supply voltage has settled.

Claims

1. A power saving integrated circuit having a power saving mode function, comprising:

a power supply which supplies a power supply voltage;

an operating circuit having a memory which stores an operating condition of the operating circuit, wherein a supply of the power supply voltage to the operating circuit is interrupted when the integrated circuit is in power saving mode;

a switching circuit which switches the supply of the power supply voltage to the operating circuit; and

a power control circuit having a first register which receives and stores an operating condition signal indicating the operating condition, and a counter continues to output a reset signal during a reset delay period which is set in accordance with the operating condition signal.

2. The power saving integrated circuit according to claim 1, wherein the reset delay period is equal to the sum of a shortest rise time of power supply voltage and a reset period to reset the counter after the power supply voltage has settled.

3. The power saving integrated circuit according to claim 1, wherein the counter continues to output the reset signal from a release of the interruption of the supply of the power supply voltage until a termination of the reset delay period.

4. The power saving integrated circuit according to claim 1, wherein the counter continues to output the reset signal from a release of the interruption of the supply of the power supply voltage until the power supply voltage level reaches an operating voltage level of the operating circuit.

5. The power saving integrated circuit according to claim 1, wherein the power saving circuit further comprises:

a dividing counter which divides a clock signal and outputs a divided clock signal to the operating circuit, in accordance with the operating condition signal which is stored in the first register.

6. The power saving integrated circuit according to claim 1, wherein the power control circuit further comprises:

a second register which receives and stores the operating condition; and

a dividing counter which divides a clock signal and outputs a divided clock signal to the operating circuit, in accordance with the operating condition signal which is stored in the second register.

7. A power saving integrated circuit having a power saving mode function, comprising:

a power supply which supplies a power supply voltage;

an operating circuit having a memory which stores an operating condition of the operating circuit, wherein a supply of the power supply voltage to the operating circuit is interrupted when the integrated circuit is in power saving mode, and wherein the operating condition includes a reset delay period which is set in accordance with an operating voltage level of the operating circuit and a clock frequency which is correlated with the reset delay period;

a switching circuit which switches the supply of the power supply voltage to the operating circuit; and

a first register which receives and stores the reset delay period;

a second register which receives and stores the clock frequency;

a counter which continues to output a reset signal to the operating circuit in accordance with the reset delay period; and

a dividing counter which divides a clock signal and outputs a divided clock signal to the operating circuit.

8. The power saving integrated circuit according to claim 7, wherein the reset delay period is equal to the sum of a shortest rise time of power supply voltage and a reset period to reset the counter after the power supply voltage has settled.

9. The power saving integrated circuit according to claim 7, wherein the counter continues to output the reset signal from a release of the interruption of the supply of the power supply voltage until a termination of the reset delay period.

10. The power saving integrated circuit according to claim 7, wherein the counter continues to output the reset signal from a release of the interruption of the supply of the power supply voltage until the power supply voltage level reaches the operating voltage level of the operating circuit.

11. A method of controlling a power saving integrated circuit having a normal active mode and a power saving mode, comprising:

detecting a first signal which shows a transition from the normal active mode to the power saving mode;

interrupting supply of a power supply voltage to an operating circuit in the integrated circuit;

storing an operating condition signal which indicates the operating condition;

outputting a reset signal to the operating circuit in accordance with the stored operating condition signal;

starting a reset delay period in response to a release signal, which indicates to release the interruption of the supply of the power supply voltage, the reset delay period being set in accordance with the operating condition signal; and

stopping the output of the reset signal after a termination of the reset delay period.

12. The method according to claim 11, wherein the output of the reset signal continues from a release of the interruption of the supply of the power supply voltage until the termination of the reset delay period.

13. The method according to claim 11, wherein the output of the reset signal continues from a release of the interruption of the supply of the power supply voltage until the power supply voltage level reaches an operating voltage level of the operating circuit.

14. The method according to claim 11 further comprises:

dividing a clock signal and outputting a divided clock signal to the operating circuit, in accordance with the operating condition signal which is stored in the first register.

15. The method according to claim 11, further comprises:

receiving and storing the operating condition signal of the operating circuit; and

dividing a clock signal and outputting a divided clock signal to the operating circuit, in accordance with the operating condition which is stored in the second register.

17. The method according to claim 16, wherein the output of the reset signal continues from a release of the interruption of the supply of the power supply voltage until a termination of the reset delay period.

18. The method according to claim 16, wherein the output of the reset signal continues from a release of the interruption of the supply of the power supply voltage until the power supply voltage level reaches the operating voltage level of the operating circuit.

16. A method of controlling a power saving integrated circuit having a normal active mode and a power saving mode, comprising:

detecting a first signal which shows a transition from the normal active mode to the power saving mode;

interrupting supply of a power supply voltage to an operating circuit in the integrated circuit;

storing a reset delay period which is set in accordance with an operating voltage level of the operating circuit;

storing a clock frequency which is correlation with the reset delay period;

outputting a reset signal to the implementing circuit in accordance with the stored reset delay period;

dividing a clock signal and outputting a divided clock signal to the operating circuit in accordance with the stored clock frequency;

releasing the power saving mode in response to a release signal which indicates a time to release the interruption of the supply of the power supply voltage; and

interrupting the output of the reset signal after a termination of the reset delay period.