Nonvolatile semiconductor memory

• US 20020149974A1
• Filed: 06/17/2002
• Published: 10/17/2002
• Est. Priority Date: 07/12/2000
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Hitachi, Ltd.
• Inventors: Sato, Hiroshi, Noda, Satoshi, Shigematsu, Koji, Kubono, Shoji, Manita, Kiichi
• Granted Patent: US 6,567,319 B2
• Time in Patent Office: Days
• US Class Current: 365/189.11
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 5/145 Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor G11C5/141 takes precedence

Abstract

Disclosed is a semiconductor memory having an internal booster, such as a flash memory, in which a situation that the program cannot escape from a writing operation can be avoided, and the writing operation can be promptly finished according to the level of an external source voltage. This semiconductor memory having an internal booster has a voltage detecting circuit (limiter LM) for detecting whether a boosted voltage has reached a predetermined potential or not and a timer capable of counting predetermined time. A control circuit applies the boosted voltage to a selected memory cell when the voltage detecting circuit detects that the boosted voltage has reached the predetermined potential and, when it is detected on the basis of counting information of the timer that the predetermined time has elapsed since the booster started the boosting operation, the control circuit applies the boosted voltage to the selected memory cell even if the boosted voltage generated by the booster has not reached the predetermined potential yet.

Claims

1. A semiconductor memory having a plurality of memory cells and a booster for generating a boosted voltage on the basis of a source voltage supplied from the outside, for applying said boosted voltage to a selected memory cell when the voltage generated by the booster reaches a predetermined level, comprising:

a voltage detecting circuit for detecting whether said boosted voltage has reached a predetermined potential or not;

a control circuit capable of controlling start and stop of a boosting operation of said booster; and

a timer capable of counting predetermined time,

wherein said control circuit applies said boosted voltage to a selected memory cell when said voltage detecting circuit detects that said boosted voltage has reached the predetermined potential and, when it is detected on the basis of counting information of said timer that the predetermined time has elapsed since said booster started the boosting operation, said control circuit applies the boosted voltage to said selected memory cell even if the boosted voltage generated by said booster has not reached the predetermined potential yet.

2. The semiconductor memory according to claim 1, further comprising switching means for supplying or interrupting said boosted voltage, wherein said switching means receives a control signal from said control circuit and applies said boosted voltage to said selected memory cell.

3. The semiconductor memory according to claim 2, further comprising a clock generating circuit for generating an internal clock signal.

4. The semiconductor memory according to claim 3, wherein said booster operates on the basis of a clock signal for boosting generated by said clock generating circuit, and said timer operates on the basis of a clock signal for counting generated by said clock generating circuit.

5. The semiconductor memory according to claim 4, further comprising a plurality of word lines, wherein each of said plurality of memory cells is connected to a corresponding word line, and said boosted voltage is applied to a word line to which the selected memory cell is coupled.

6. The semiconductor memory according to claim 5, wherein said booster has a positive voltage generating circuit for generating a positive high voltage on the basis of a source voltage from the outside and a negative voltage generating circuit for generating a negative high voltage on the basis of the source voltage from the outside.

7. The semiconductor memory according to claim 6, wherein each of said plurality of memory cells has a threshold voltage corresponding to data to be stored.

8. The semiconductor memory according to claim 7, wherein data is written/erased to/from each of said plurality of memory cells by using a tunnel phenomenon.

9. A semiconductor memory having a plurality of memory cells each having a threshold voltage corresponding to data to be stored, a plurality of bit lines, a plurality of data latches provided for the bit lines, and a booster for generating a boosted voltage on the basis of a source voltage supplied from the outside, each of said plurality of memory cells being coupled to a corresponding bit line, said boosted voltage being applied to said memory cell selected when said boosted voltage reaches a predetermined potential, and data being rewritten to the memory cell in accordance with data latched by said data latch, comprising:

a voltage detecting circuit for detecting whether said boosted voltage has reached a predetermined potential or not;

a control circuit capable of controlling start and stop of a boosting operation of said booster; and

a timer capable of counting predetermined time,

wherein said control circuit applies said boosted voltage to a selected memory cell when said voltage detecting circuit detects that said boosted voltage has reached the predetermined potential and, when it is detected on the basis of counting information of said timer that the predetermined time has elapsed since said booster started the boosting operation, said control circuit applies the boosted voltage to said selected memory cell even if the boosted voltage generated by said booster has not reached the predetermined potential yet.

10. The semiconductor memory according to claim 9, wherein each of said memory cells stores multi-value information by having any one of a plurality of threshold voltages.

11. The semiconductor memory according to claim 10, further comprising switching means for supplying or interrupting said boosted voltage, wherein said switching means receives a control signal from said control circuit and applies said boosted voltage to said selected memory cell.

12. The semiconductor memory according to claim 11, further comprising a clock generating circuit for generating an internal clock signal,

wherein said booster operates on the basis of a clock signal for boost generated by said clock generating circuit, and said timer operates on the basis of a clock signal for counting generated by said clock generating circuit.

13. The semiconductor memory according to claim 12, further comprising a plurality of word lines, wherein each of said plurality of memory cells is connected to a corresponding word line, and said boosted voltage is applied to a word line to which the selected memory cell is coupled.

14. The semiconductor memory according to claim 13, wherein a second voltage boosted by said booster in accordance with data latched by said data latch and reached a predetermined potential is applied to said bit line, and said control circuit reserves activation of said timer until said second voltage reaches the predetermined potential.

16. A system according to claim 15,

wherein said nonvolatile memory device is removable from said system.

17. A system according to claim 15,

wherein said boosted voltage is used for programming data to said nonvolatile memory array.

15. A system supplied with voltage from outside, comprising a controller and a nonvolatile memory device which includes:

a nonvolatile memory array;

a voltage generating circuit generating a boosted voltage from said supplied voltage and supplying said boosted voltage to said nonvolatile memory array, and

wherein said voltage generating circuit includes a timer circuit and voltage detecting circuit,

wherein said timer circuit detects a first event which is a predetermined time having passed from a start of voltage boosting,

wherein said voltage detecting circuit detects a second event which is a voltage level of said boosted voltage having reached a predetermined voltage level, and

wherein said voltage generating circuit starts supplying said boosted voltage when said timer circuit detects said first event or said voltage detecting circuit detects said second event.

18. A system comprising:

a voltage supply source;

a controller; and

a nonvolatile memory device,

wherein said voltage supply source supplies voltage to said controller and said nonvolatile memory device,

wherein said controller is capable of supplying a program command to said nonvolatile memory device,

wherein said nonvolatile memory device includes a plurality of nonvolatile memory cells and a voltage generating circuit and carries out a data storing operation for storing data to ones of said nonvolatile memory cells responsive to said program command,

wherein said voltage generating circuit comprises a timer circuit, a voltage detecting circuit and a voltage output circuit and generates a boost voltage boosted from said supplied voltage,

wherein said timer circuit outputs a first signal to said voltage output circuit when a predetermined time has passed from a start of voltage boosting,

wherein said voltage detecting circuit outputs a second signal to said voltage output circuit when a voltage level of said boost voltage has reached a predetermined voltage level, and

wherein said voltage output circuit outputs said boost voltage to said nonvolatile memory cells when receiving said first signal or said second signal.