RF power device and method of manufacturing the same

• US 20020151124A1
• Filed: 05/31/2002
• Published: 10/17/2002
• Est. Priority Date: 11/04/2000
• Status: Active Grant

• Current Assignee: Cheon-Soo Kim, Hyun-Kyu Yu, Jung-Woo Park, Nam Hwang
• Original Assignee: Cheon-Soo Kim, Hyun-Kyu Yu, Jung-Woo Park, Nam Hwang
• Inventors: Park, Jung-Woo, Yu, Hyun-Kyu, Kim, Cheon-Soo, Hwang, Nam
• Granted Patent: US 6,620,667 B2
• Time in Patent Office: Days
• US Class Current: 438/197
• CPC Class Codes: H01L 29/1087 characterised by the contact structure of the substrate region, e.g. for controlling or preventing bipolar effect
• CPC Class Codes: H01L 29/4175 for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An HF power device in an HF transistor includes a semiconductor layer as a first conductive type, a field area formed in a trench structure on one side of the semiconductor layer, gate electrode formed on a given surface of the semiconductor layer, a channel layer as a second conductive type laterally diffused from the field area to a width containing both sides of the gate electrode, and formed on the surface of the semiconductor layer, a source area as the second conductive type formed within the channel layer between one side of the gate electrode and the field area, a drain area as the second conductive type formed on the surface of the semiconductor layer with a given interval from another side of the gate electrode, a sinker as the first conductive type provided as a column shape of a trench structure for dividing into two source areas by a piercing through the source area, and connected to the semiconductor layer, an LDD area as the second conductive type formed on the surface of the semiconductor layer between the drain area and the gate electrode, first metal electrode contacted with the source area divided into two source areas and electrically connected to the semiconductor layer through the sinker, and second metal electrode coupled with the drain area.

Claims

1. A method of manufacturing an HF power device comprising the steps of:

forming a semiconductor layer as a first conductive type on a semiconductor substrate as the first conductive type;

etching the semiconductor layer by a given depth and forming a first trench;

doping impurity of the first conductive type on the neighborhood of the first trench and forming a first impurity layer as the first conductive type connected to the semiconductor substrate;

burying a conduction film as the first conductive type into the first trench;

etching the semiconductor layer by a given depth and forming a second trench with a constant interval from the first trench;

forming a field oxide film buried into the second trench;

forming gate electrode on a given surface of the semiconductor layer;

forming a source area of a second conductive type on the surface of the semiconductor layer so as to be structurally self-aligned on one side of the gate electrode and be structurally pierced by the conduction film;

forming a drain area as the second conductive type on the surface of the semiconductor layer with a given interval from another side of the gate electrode;

forming an LDD area of the second conductive type on the surface of the semiconductor layer between the drain area and the gate electrode;

forming first metal electrode having a width which reaches the source area and the gate electrode; and

forming second metal electrode electrically connected to the LDD area.

2. The method of claim 1, wherein in the first trench forming step, said semiconductor layer is etched by a depth reaching the semiconductor substrate.

3. The method of claim 1, wherein in the first trench forming step, one or a plural number of trenches are formed by etching the semiconductor layer.

4. The method of claim 3, wherein said first impurity layer is formed on the plural number of trenches with the conductive type same as the substrate of the first conductive type, and neighboring first impurity layers are coupled with each other to form a column shape.

5. The method of claim 1, wherein the second trench forming step is performed by etching the semiconductor layer and forming one or the plural number of trenches.

6. The method of claim 1, wherein the field oxide film is performed by growing the thermal oxide film in the inside of said second trench.

7. The method of claim 1, wherein the field oxide film forming the step comprises the steps of:

covering the semiconductor layer of the first conductive type containing the second trench with an oxide film; and

forming the field oxide film buried into the second trench by executing a chemical mechanical polishing for the covering film.