RF power device and method of manufacturing the same
First Claim
1. A method of manufacturing an HF power device comprising the steps of:
- forming a semiconductor layer as a first conductive type on a semiconductor substrate as the first conductive type;
etching the semiconductor layer by a given depth and forming a first trench;
doping impurity of the first conductive type on the neighborhood of the first trench and forming a first impurity layer as the first conductive type connected to the semiconductor substrate;
burying a conduction film as the first conductive type into the first trench;
etching the semiconductor layer by a given depth and forming a second trench with a constant interval from the first trench;
forming a field oxide film buried into the second trench;
forming gate electrode on a given surface of the semiconductor layer;
forming a source area of a second conductive type on the surface of the semiconductor layer so as to be structurally self-aligned on one side of the gate electrode and be structurally pierced by the conduction film;
forming a drain area as the second conductive type on the surface of the semiconductor layer with a given interval from another side of the gate electrode;
forming an LDD area of the second conductive type on the surface of the semiconductor layer between the drain area and the gate electrode;
forming first metal electrode having a width which reaches the source area and the gate electrode; and
forming second metal electrode electrically connected to the LDD area.
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Accused Products
Abstract
An HF power device in an HF transistor includes a semiconductor layer as a first conductive type, a field area formed in a trench structure on one side of the semiconductor layer, gate electrode formed on a given surface of the semiconductor layer, a channel layer as a second conductive type laterally diffused from the field area to a width containing both sides of the gate electrode, and formed on the surface of the semiconductor layer, a source area as the second conductive type formed within the channel layer between one side of the gate electrode and the field area, a drain area as the second conductive type formed on the surface of the semiconductor layer with a given interval from another side of the gate electrode, a sinker as the first conductive type provided as a column shape of a trench structure for dividing into two source areas by a piercing through the source area, and connected to the semiconductor layer, an LDD area as the second conductive type formed on the surface of the semiconductor layer between the drain area and the gate electrode, first metal electrode contacted with the source area divided into two source areas and electrically connected to the semiconductor layer through the sinker, and second metal electrode coupled with the drain area.
16 Citations
7 Claims
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1. A method of manufacturing an HF power device comprising the steps of:
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forming a semiconductor layer as a first conductive type on a semiconductor substrate as the first conductive type;
etching the semiconductor layer by a given depth and forming a first trench;
doping impurity of the first conductive type on the neighborhood of the first trench and forming a first impurity layer as the first conductive type connected to the semiconductor substrate;
burying a conduction film as the first conductive type into the first trench;
etching the semiconductor layer by a given depth and forming a second trench with a constant interval from the first trench;
forming a field oxide film buried into the second trench;
forming gate electrode on a given surface of the semiconductor layer;
forming a source area of a second conductive type on the surface of the semiconductor layer so as to be structurally self-aligned on one side of the gate electrode and be structurally pierced by the conduction film;
forming a drain area as the second conductive type on the surface of the semiconductor layer with a given interval from another side of the gate electrode;
forming an LDD area of the second conductive type on the surface of the semiconductor layer between the drain area and the gate electrode;
forming first metal electrode having a width which reaches the source area and the gate electrode; and
forming second metal electrode electrically connected to the LDD area. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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Specification