Semiconductor device having a multilayer interconnection structure

• US 20020151190A1
• Filed: 03/26/2002
• Published: 10/17/2002
• Est. Priority Date: 03/24/1998
• Status: Active Grant

• Current Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Original Assignee: Fujitsu Limited
• Inventors: Kudo, Hiroshi, Ikeda, Masanobu, Ohkura, Yoshiyuki, Watanabe, Kenichi
• Granted Patent: US 7,041,586 B2
• Time in Patent Office: Days
• US Class Current: 438/780
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76819 Smoothing of the dielectric planarisation of insulating materials per se H01L21/31051
• CPC Class Codes: H01L 21/7682 the dielectric comprising air gaps
• CPC Class Codes: H01L 21/76829 characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76835 Combinations of two or more different dielectric layers having a low dielectric constant H01L21/76832 takes precedence
• CPC Class Codes: H01L 21/76837 Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics
• CPC Class Codes: H01L 21/7684 Smoothing; Planarisation
• CPC Class Codes: H01L 21/76882 Reflowing or applying of pressure to better fill the contact hole
• CPC Class Codes: H01L 23/5222 Capacitive arrangements or effects of, or between wiring layers other capacitive arrangements H01L23/642
• CPC Class Codes: H01L 23/53228 the principal metal being copper
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 23/53295 Stacked insulating layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/12044 OLED

Abstract

A semiconductor device includes a multilayer interconnection structure including an organic interlayer insulation film in which a conductor pattern is formed by a damascene process, wherein the organic interlayer insulation film carries thereon an organic spin-on-glass film.

Claims

1. A method of fabricating a semiconductor device, comprising the steps of:

forming an interlayer insulation film on a substrate;

forming an organic spin-on-glass film on said interlayer insulation film;

patterning said organic spin-on-glass film and said interlayer insulation film to form a depression such that said depression penetrates through said organic spin-on-glass film and reaches said interlayer insulation film;

depositing a conductor layer on said organic spin-on-glass film so as to fill said depression; and

removing a part of said conductor layer locating above said organic spin-on-glass film by a chemical mechanical polishing process, to form a conductor pattern filling said depression, said chemical mechanical polishing process being conducted while using said organic spin-on-glass film as a polishing stopper.

2. A method as claimed in claim 1, wherein said interlayer insulation film is formed of a hydrocarbon polymer compound.

3. A method as claimed in claim 1, wherein said interlayer insulation film is formed of an aromatic polymer compound.

4. A method as claimed in claim 1, wherein said conductor layer is formed of Cu.

5. A method as claimed in claim 4, further comprising the step, after said step of forming said depression but before said step of forming said conductor layer, of covering a surface of said depression by a film of a refractory metal compound in conformity with a shape of said depression.

6. A method as claimed in claim 1, wherein said depression is formed so as to penetrate through said interlayer insulation film.

7. A method as claimed in claim 1, further comprising the steps of:

forming, after said step of forming said conductor pattern, a planarized insulation film on said organic spin-on-glass film;

forming a depression in said planarized insulation film; and

forming another conductor pattern such that said another conductor pattern fills said depression in said planarized insulation film.

8. A method as claimed in claim 7, wherein said step of forming said planarized insulation film includes the step of applying said planarized insulation film in the form of a liquid such that said liquid covers said conductor pattern.

9. A method as claimed in claim 7, wherein said step of forming said planarized insulation film includes the steps of:

forming another insulation film on said organic spin-on-glass film; and

planarizing said another insulation film by a chemical mechanical polishing process.

10. A method as claimed in claim 1, further comprising, after said step of forming said conductor pattern, the steps of:

forming a first planarized interlayer insulation film on said organic spin-on-glass film by applying said first planarized interlayer insulation film in the form of a liquid;

forming a second planarized interlayer insulation film on said first planarized interlayer insulation film;

forming another depression in said second planarized interlayer insulation film such that said another depression penetrates through said second planarized interlayer insulation film and reaches said first planarized interlayer insulation film; and

forming another conductor pattern so as to fill said another depression by a damascene process.

11. A method of fabricating a semiconductor device, comprising the steps of:

forming an interlayer insulation film on a substrate;

forming a groove in said interlayer insulation film;

forming a conductor layer on said interlayer insulation film so as to fill said groove;

removing a part of said conductor layer covering said interlayer insulation film by a chemical mechanical polishing process, to form a conductor pattern filling said groove; and

applying an insulation film of a liquid form on said interlayer insulation film, such that said insulation film covers said conductor pattern.

14. A semiconductor device as claimed in claim 13, wherein said conductor pattern is formed of Cu.

15. A semiconductor device as claimed in claim 13, wherein said interlayer insulation film is formed of a hydrocarbon polymer compound.

16. A semiconductor device as claimed in claim 13, wherein said interlayer insulation film is formed of an aromatic polymer compound.

17. A semiconductor device as claimed in claim 13, further comprising a conductor film between said depression and said conductor pattern, said conductor film covering said depression in conformity with a shape of said depression.

18. A semiconductor device as claimed in claim 13, wherein said depression penetrates through said interlayer insulation film.

20. A semiconductor device as claimed in claim 19, wherein said second interlayer insulation film is formed of an organic insulation film.

21. A semiconductor device as claimed in claim 19, wherein said second interlayer insulation film includes a first film of an organic insulation film having a planarized top surface, and a second film formed on said first film.

22. A semiconductor device as claimed in claim 19, wherein said first conductor pattern is repeated in said first interlayer insulation film with a first pitch, and said second conductor pattern is repeated in said second interlayer insulation film with a second pitch smaller than said first pitch.

23. A semiconductor device as claimed in claim 19, wherein said first conductor pattern extends in said first interlayer insulation film in a first direction and wherein said second conductor pattern extends in said second interlayer insulation film in a second direction different from said first direction.

24. A semiconductor device as claimed in claim 19, wherein said first conductor pattern extends in said first interlayer insulation film in a first direction and wherein said second conductor pattern extends in said second interlayer insulation film in said first direction.

25. A semiconductor device as claimed in claim 19, wherein said second interlayer insulation film is an inorganic insulation film having a planarized top surface.

12. A method of fabricating a semiconductor device, comprising the steps of:

forming a first interlayer insulation film on a substrate;

forming a groove in said first interlayer insulation film;

forming a conductor layer on said first interlayer insulation film so as to fill said groove;

removing a part of said conductor layer covering said first interlayer insulation film by a chemical mechanical polishing process, to form a conductor pattern filling said groove;

forming a second interlayer insulation film on said first interlayer insulation film so as to cover said conductor pattern; and

planarizing said second interlayer insulation film by a chemical mechanical polishing process.

13. A semiconductor device, comprising:

a substrate;

an interlayer insulation film formed on said substrate;

another insulation film formed on said interlayer insulation film;

a depression penetrating through said another insulation film and reaching said interlayer insulation film; and

a conductor pattern filling said depression;

said another insulation film being formed of an organic spin-on-glass.

19. A semiconductor device, comprising:

a substrate;

a first interlayer insulation film formed on said substrate;

a first depression formed in said first interlayer insulation film;

a first conductor pattern filling said first depression;

a second interlayer insulation film formed on said first interlayer insulation film so as to cover said first conductor pattern, said second interlayer insulation film having a planarized surface;

a second depression formed in said second interlayer insulation film; and

a second conductor pattern filling said second depression.